riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Test] Add superLUT test case to CI

This commit is contained in:
tangxifan 2021-02-09 21:15:21 -07:00
parent 22e675148e
commit be24c904af
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.github/workflows/fpga_verilog_reg_test.sh vendored
View File

@ -14,6 +14,9 @@ run-task fpga_verilog/lut_design/single_mode --debug --show_thread_logs
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
run-task fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
echo -e "Testing Verilog generation for LUTs: fracturable LUT4 with embedded carry logic";
run-task fpga_verilog/lut_design/frac_lut4_arith --debug --show_thread_logs
echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 ";
run-task fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs