From be24c904afa3d8a381c5dbbb17e7dae7f9bf63d0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Feb 2021 21:15:21 -0700 Subject: [PATCH] [Test] Add superLUT test case to CI --- .github/workflows/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/.github/workflows/fpga_verilog_reg_test.sh index 7b7aad6b0..2f5b917dc 100755 --- a/.github/workflows/fpga_verilog_reg_test.sh +++ b/.github/workflows/fpga_verilog_reg_test.sh @@ -14,6 +14,9 @@ run-task fpga_verilog/lut_design/single_mode --debug --show_thread_logs echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 "; run-task fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs +echo -e "Testing Verilog generation for LUTs: fracturable LUT4 with embedded carry logic"; +run-task fpga_verilog/lut_design/frac_lut4_arith --debug --show_thread_logs + echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 "; run-task fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs