tangxifan
|
c7a9a4e896
|
[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
|
2021-02-22 15:01:50 -07:00 |
|
tangxifan
|
ca135f3325
|
[Arch] Add flagship architecture with 8-clock
|
2021-02-22 15:01:18 -07:00 |
|
tangxifan
|
2e2b1cb6e7
|
[Test] Use hetergenenous FPGA architecture in quicklogic tests
|
2021-02-22 13:41:04 -07:00 |
|
tangxifan
|
1c09c55e9f
|
[Arch] Add hetergenenous 8-clock FPGA architecture
|
2021-02-22 13:38:50 -07:00 |
|
tangxifan
|
b3fed683f9
|
[Test] Deploy test to CI
|
2021-02-22 12:43:30 -07:00 |
|
tangxifan
|
bc30f62c5a
|
[Test] Add test for sdc controller
|
2021-02-22 12:41:53 -07:00 |
|
tangxifan
|
60dc194d8f
|
[Test] Bug fix in the 5clock test case
|
2021-02-22 11:46:23 -07:00 |
|
tangxifan
|
71e0026a50
|
[Test] Add new test for 5-clock counter to quicklogic tests
|
2021-02-22 11:32:17 -07:00 |
|
tangxifan
|
2bb588dacf
|
[Flow] Add a new script for generating bitstream for multi-clock architectures
|
2021-02-22 11:31:24 -07:00 |
|
tangxifan
|
77896379e2
|
[Arch] Add simulation setting for 8-clock architectures
|
2021-02-22 11:10:03 -07:00 |
|
tangxifan
|
16debe49f6
|
[Arch] Add more comments on the 4 clock simulation setting file
|
2021-02-22 11:04:34 -07:00 |
|
tangxifan
|
0ac75723af
|
[Arch] Add new architecture with 8 clocks
|
2021-02-22 11:00:45 -07:00 |
|
tangxifan
|
b9c2564a7e
|
[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
|
2021-02-22 10:49:21 -07:00 |
|
tangxifan
|
bc8aa0ebc6
|
[Test] Remove routing test from quicklogic's flow test
|
2021-02-22 10:22:47 -07:00 |
|
tangxifan
|
2dbdc2644f
|
[Benchmark] Remove replicate micro benchmarks
|
2021-02-22 10:22:19 -07:00 |
|
tangxifan
|
9b6b2068ee
|
[Test] Move MCNC test to benchmark sweep test group
|
2021-02-22 10:18:34 -07:00 |
|
tangxifan
|
c1f4a434e4
|
[Doc] Update README for the regression test tasks
|
2021-02-22 10:17:02 -07:00 |
|
tangxifan
|
0384c4c61e
|
Merge branch 'master' into dev
|
2021-02-22 09:49:03 -07:00 |
ganeshgore
|
4315660bf1
|
Merge pull request #245 from lnis-uofu/dev
Throw fatal error when the number of configurable region is different between fabric key and architecture definition
|
2021-02-22 09:48:23 -07:00 |
|
tangxifan
|
d6a02a985e
|
Merge pull request #248 from lnis-uofu/add_quicklogic_tests
Disabling verilog testbench generation for quicklogic tests
|
2021-02-22 09:02:29 -07:00 |
Lalit Sharma
|
d842026672
|
Disabling verilog testbench generation for quicklogic tests
|
2021-02-21 21:58:23 -08:00 |
Lalit Narain Sharma
|
be5e0cdea9
|
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
|
2021-02-22 09:50:26 +05:30 |
|
Lalit Sharma
|
576e6753f6
|
Removing 2 more tests which are variant of and design
|
2021-02-19 09:11:19 -08:00 |
|
Lalit Sharma
|
d4c5a5655a
|
Removing blif file as well as and2 testcase
|
2021-02-19 08:55:17 -08:00 |
|
Lalit Sharma
|
6de0954ca5
|
Uncommenting all benchmarks except 2 that requires multiple clocks
|
2021-02-19 08:40:26 -08:00 |
|
tangxifan
|
01b9bf2a02
|
[Doc] Update num_region XML for config protocol
|
2021-02-18 21:58:30 -07:00 |
|
tangxifan
|
e6091fb3ff
|
[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
|
2021-02-18 21:56:30 -07:00 |
|
tangxifan
|
bcd8256c59
|
Merge pull request #243 from lnis-uofu/dev
Bug fix for truth table creation for wired LUT created by repacking
|
2021-02-18 20:44:02 -07:00 |
|
tangxifan
|
e08ac1a41e
|
[Test] Deploy synthesizable verilog test to CI
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
e19fc15fec
|
[Test] bug fix in test case
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
affc8cbbc4
|
[Test] Deploy test to CI
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
2e88b035ed
|
[Test] Add wire LUT repacker test case
|
2021-02-18 19:37:44 -07:00 |
|
tangxifan
|
1f097abe99
|
[Benchmark] Add micro benchmark for FIR filter
|
2021-02-18 19:37:44 -07:00 |
|
tangxifan
|
a5b8b2a64a
|
[Tool] Use dedicated function to identify wire LUT created by repacker
|
2021-02-18 19:37:44 -07:00 |
|
tangxifan
|
aae03482f5
|
[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
|
2021-02-18 19:37:17 -07:00 |
|
ganeshgore
|
122218dfd3
|
Merge pull request #244 from lnis-uofu/synth_verilog_test_deployment
Deploy synthesizable verilog test to CI
|
2021-02-18 10:46:19 -07:00 |
|
Lalit Sharma
|
69cdc11ea5
|
Uncommenting the tests that are running fine
|
2021-02-18 04:17:12 -08:00 |
|
tangxifan
|
a06e7e6c80
|
Merge branch 'master' into dev
|
2021-02-17 19:46:09 -07:00 |
|
tangxifan
|
9004e28d47
|
Merge branch 'master' into synth_verilog_test_deployment
|
2021-02-17 19:45:35 -07:00 |
|
tangxifan
|
1a23f76bd0
|
Merge pull request #242 from lnis-uofu/gg_ci_cd_dev
[Bugfix] Docker regression using master regression scripts
|
2021-02-17 19:21:46 -07:00 |
|
tangxifan
|
47cb1cc2d4
|
[Test] Deploy synthesizable verilog test to CI
|
2021-02-17 16:13:15 -07:00 |
|
tangxifan
|
61012897cd
|
[Tool] Bug fix for truth table creation for wired LUT created by repacking algorithm
|
2021-02-17 15:31:20 -07:00 |
|
Ganesh Gore
|
808df8a87e
|
[Bugfix] Docker regression using master regression scripts
|
2021-02-17 13:23:45 -07:00 |
|
tangxifan
|
d85d6e964e
|
Merge pull request #227 from watcag/master
Standard-cell flow
|
2021-02-17 10:11:34 -07:00 |
|
Lalit Sharma
|
7ee01711c2
|
Merge remote-tracking branch 'origin/master' into add_quicklogic_tests
|
2021-02-17 00:06:59 -08:00 |
|
ganeshgore
|
515527f7f1
|
Merge pull request #238 from lnis-uofu/dev
Move regression test scripts from workflow to openfpga_flow
|
2021-02-17 00:15:03 -07:00 |
|
Lalit Sharma
|
44a979288b
|
Adding quicklogic tests and updating the corresponding conf file to run them
|
2021-02-16 23:08:38 -08:00 |
|
tangxifan
|
a819375f69
|
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
|
2021-02-16 16:53:13 -07:00 |
|
tangxifan
|
2c2e493739
|
[Test] Remove quicklogic test from basic tests
|
2021-02-16 12:29:10 -07:00 |
|
tangxifan
|
9c19e2b365
|
[Test] Move regression test scripts from workflow to openfpga_flow
|
2021-02-16 11:55:47 -07:00 |