ebe66dea35
Bumping up latest yosys changes related to adder tech mapping
2021-02-03 14:30:06 +05:30
2c06960e4f
[Benchmark] Add subckt definition to micro benchmark and2.eblif
2021-02-02 15:51:16 -07:00
021520783b
[Arch] Add dummy timing info to adder_lut4 and carry_follower model
2021-02-02 15:49:43 -07:00
dc320182b0
[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
2021-02-02 15:04:43 -07:00
8e36ed1ab6
[Test] Update task configuration to use and2 eblif
2021-02-02 15:01:15 -07:00
62803dc044
[Benchmark] Add eblif example for and2 benchmark
2021-02-02 14:59:31 -07:00
5e2847bc41
[Test] Update test case to use eblif file
2021-02-02 09:33:41 -07:00
39e6f62d91
[Benchmark] Use eblif in naming the adder_8 micro benchmark
2021-02-02 09:32:42 -07:00
d3397f6936
[Script] Remove activity from bitstream setting example script
2021-02-02 09:25:36 -07:00
9ff5e7926b
[Test] Update test case to use the adder benchmark
2021-02-02 09:24:39 -07:00
7f14dfbe87
[Script] Add example script to use bitstream setting
2021-02-02 09:18:08 -07:00
d83158654c
[Doc] Add a draft documentation about the bitstream setting
2021-02-01 22:33:17 -07:00
0c409b5bcc
[Tool] Add bitstream annotation support
2021-02-01 20:49:36 -07:00
faabdab815
[Tool] Remove redundant tab in bitstream setting writer
2021-02-01 18:04:21 -07:00
d5b1cc5ec7
[Tool] Bug fix in parser for bitstream settings
2021-02-01 18:01:42 -07:00
f102e84497
[Tool] Add bitstream setting file to openfpga library
2021-02-01 17:43:46 -07:00
04594cb7ab
[Test] Adapt bitstream annotatin file to parser's requirement
2021-02-01 17:38:36 -07:00
280c9620aa
[Test] Add an example bitstream annotation file
2021-02-01 16:01:21 -07:00
a6354fab7c
[Arch] Decide to move external bitstream definition to a separated XML file
2021-02-01 15:57:44 -07:00
df88e2adc0
[Arch] Add an example definition of external bitstream to openfpga arch with soft adder
2021-02-01 14:26:11 -07:00
10302752a7
[Arch] Bug fix in architecture. Now soft adder modes are accepted
2021-02-01 13:43:39 -07:00
d8927e12e8
[Arch] Add soft adder operating mode to test architecture
2021-02-01 12:25:37 -07:00
7f0f7a1c70
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
2021-02-01 12:05:04 -07:00
b215b868c1
[HDL] Bug fix in HDL netlist due to port name mismatching
2021-02-01 11:35:25 -07:00
e4abe263c3
[Arch] Bug fix
2021-02-01 11:29:27 -07:00
fb05e1a938
[Arch] bug fix due to using openfpga cell library
2021-02-01 11:27:21 -07:00
940dce469a
[Test] Bug fix for test case configuration
2021-02-01 11:19:47 -07:00
a80acfb547
[Test] Add new test case to CI script
2021-02-01 11:16:12 -07:00
af630dab1e
[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
2021-02-01 10:53:38 -07:00
9cce411eda
[Test] Add adder test cases
2021-02-01 10:42:24 -07:00
0eb949b85a
[Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA
2021-02-01 10:34:32 -07:00
e0e2506e32
[HDL] Remove redundant comments
2021-02-01 10:33:08 -07:00
39543f7945
[HDL] Add carry mux2 to cell library
2021-02-01 10:23:46 -07:00
6ede799c16
[Arch] Add openfpga architecture for the QLSOFA
2021-02-01 10:15:35 -07:00
f51aaae4a2
Merge pull request #208 from lnis-uofu/bump_yosys
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Bumping up yosys submodule as an option (-verilog) is added to write …
2021-02-01 10:07:25 -07:00
df05911d24
Merge branch 'master' into soft_adder_lut_support
2021-02-01 10:02:05 -07:00
0f287fb539
Bumping up yosys submodule as an option (-verilog) is added to write verilog file
2021-02-01 13:43:31 +05:30
186a0cadfb
Checking complete flow of build.yml from non master branch ( #207 )
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* [CICD] SHA extraction bug fix
* [CICD] Docker image builds but push from master
* [CICD] General cleanup
2021-01-30 09:40:53 -07:00
20aebebcf2
Merge pull request #206 from lnis-uofu/gg_ci_cd_dev
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[CICD] Added SHA tag to docker build image
2021-01-29 22:11:28 -07:00
d41ca7d2fd
Merge pull request #203 from lnis-uofu/dev
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Remove the hard requirement on signal activity file
2021-01-29 21:29:01 -07:00
52dc76c25e
[CICD] Added SHA tag to docker build image
2021-01-29 20:22:45 -07:00
af8d750170
Merge pull request #205 from lnis-uofu/gg_ci_cd_dev
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[CICD] Checking master branch in change_detect
2021-01-29 19:55:10 -07:00
9bbf214456
[Arch] Update the caravel architecture
2021-01-29 17:00:17 -07:00
30277188db
[CICD] Checking master branch in change_detect
2021-01-29 12:58:53 -07:00
0e16638dc2
[Doc] Update documentation about the changes on activity files
2021-01-29 11:49:07 -07:00
a70725b4be
Merge branch 'master' into dev
2021-01-29 11:41:40 -07:00
8b74947737
[Script] Now multi-clock openfpga shell script no longer needs activity file
2021-01-29 11:40:33 -07:00
4b77a3a574
[Tool] Now activity file is not a manadatory input of openfpga tools
2021-01-29 11:33:40 -07:00
bdf03c8b26
Bug fix on Docker build and upload on master ( #202 )
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* [CI/CD] Added force master image update option
* [CI/CD] Fixed .dockerignore while master image building
* [Test] checking correctness of source_modified flag
* [Bugfix] Fixed openfpga_flow in dockerignore
* [CICD] Added more context in dockerignore
* [CICD] Updated Dockerfile.master
* [CICD] Reverted test variables
2021-01-29 11:16:57 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
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* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
Lalit Sharma
tangxifan
ganeshgore
AurelienAlacchi