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Merge pull request #203 from lnis-uofu/dev 

Remove the hard requirement on signal activity file
This commit is contained in:
ganeshgore 2021-01-29 21:29:01 -07:00 committed by GitHub
parent af8d750170 0e16638dc2
commit d41ca7d2fd
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6 changed files with 22 additions and 12 deletions
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6
docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst
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@ -49,7 +49,8 @@ write_openfpga_simulation_setting
.. option:: --file <string> or -f <string>
Specify the file name. For example, ``--file auto_simulation_setting_echo.xml``
Specify the file name. For example, ``--file auto_simulation_setting_echo.xml``.
See details about file format at :ref:`simulation_setting`.
.. option:: --verbose
@ -62,7 +63,8 @@ link_openfpga_arch
.. option:: --activity_file <string>
Specify the signal activity file. For example, ``--activity_file counter.act``
Specify the signal activity file. For example, ``--activity_file counter.act``.
This is required when users wants OpenFPGA to automatically find the number of clocks in simulations. See details at :ref:`simulation_setting`.
.. option:: --sort_gsb_chan_node_in_edges

6
openfpga/src/annotation/annotate_simulation_setting.cpp
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@ -237,6 +237,12 @@ int annotate_simulation_setting(const AtomContext& atom_ctx,
*/
VTR_LOG("User specified the number of operating clock cycles to be inferred from signal activities\n");
/* Error out if net activity is not defined */
if (true == net_activity.empty()) {
VTR_LOG_ERROR("Signal activities are not defined!\nPlease check if activity file is given and properly generated!\n");
return CMD_EXEC_FATAL_ERROR;
}
/* Use a fixed simulation window size now. TODO: this could be specified by users */
size_t num_clock_cycles = recommend_num_sim_clock_cycle(atom_ctx,
net_activity,

5
openfpga/src/base/openfpga_context.h
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@ -67,7 +67,6 @@ class OpenfpgaContext : public Context {
const openfpga::FabricBitstream& fabric_bitstream() const { return fabric_bitstream_; }
const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; }
const openfpga::FabricGlobalPortInfo& fabric_global_port_info() const { return fabric_global_port_info_; }
const std::unordered_map<AtomNetId, t_net_power>& net_activity() const { return net_activity_; }
const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; }
const openfpga::NetlistManager& spice_netlists() const { return spice_netlists_; }
public: /* Public mutators */
@ -88,7 +87,6 @@ class OpenfpgaContext : public Context {
openfpga::FabricBitstream& mutable_fabric_bitstream() { return fabric_bitstream_; }
openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
openfpga::FabricGlobalPortInfo& mutable_fabric_global_port_info() { return fabric_global_port_info_; }
std::unordered_map<AtomNetId, t_net_power>& mutable_net_activity() { return net_activity_; }
openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; }
openfpga::NetlistManager& mutable_spice_netlists() { return spice_netlists_; }
private: /* Internal data */
@ -138,9 +136,6 @@ class OpenfpgaContext : public Context {
openfpga::NetlistManager verilog_netlists_;
openfpga::NetlistManager spice_netlists_;
/* Net activities of users' implementation */
std::unordered_map<AtomNetId, t_net_power> net_activity_;
/* Flow status */
openfpga::FlowManager flow_manager_;
};

9
openfpga/src/base/openfpga_link_arch.cpp
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@ -148,8 +148,11 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
* should be inferred from FPGA implmentation
* - When FPGA-SPICE is enabled
*/
openfpga_ctx.mutable_net_activity() = read_activity(g_vpr_ctx.atom().nlist,
cmd_context.option_value(cmd, opt_activity_file).c_str());
std::unordered_map<AtomNetId, t_net_power> net_activity;
if (true == cmd_context.option_enable(cmd, opt_activity_file)) {
net_activity = read_activity(g_vpr_ctx.atom().nlist,
cmd_context.option_value(cmd, opt_activity_file).c_str());
}
/* TODO: Annotate the number of clock cycles and clock frequency by following VPR results
* We SHOULD create a new simulation setting for OpenFPGA use only
@ -160,7 +163,7 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
*/
//openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting;
if (CMD_EXEC_FATAL_ERROR == annotate_simulation_setting(g_vpr_ctx.atom(),
openfpga_ctx.net_activity(),
net_activity,
openfpga_ctx.mutable_simulation_setting())) {
return CMD_EXEC_FATAL_ERROR;
}

2
openfpga/src/base/openfpga_setup_command.cpp
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@ -125,7 +125,7 @@ ShellCommandId add_openfpga_link_arch_command(openfpga::Shell<OpenfpgaContext>&
Command shell_cmd("link_openfpga_arch");
/* Add an option '--activity_file'*/
CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", true, "file path to the signal activity");
CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", false, "file path to the signal activity");
shell_cmd.set_option_require_value(opt_act_file, openfpga::OPT_STRING);
/* Add an option '--sort_gsb_chan_node_in_edges'*/

6
openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga
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@ -12,7 +12,11 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Note: no need to assign activity file when you used a fixed number
# of clock cycles in simulation settings
# Also, ACE2 does not support multiple clocks
# Therefore, activity file is not recommended for multi-clock fabric/implementations
link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml