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[Tool] Upgrade libopenfpga to support superLUT-related XML syntax

This commit is contained in:
tangxifan 2021-02-09 21:15:57 -07:00
parent be24c904af
commit b2984b46ee
4 changed files with 41 additions and 0 deletions
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19
libopenfpga/libarchopenfpga/src/circuit_library.cpp
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@ -964,6 +964,13 @@ size_t CircuitLibrary::port_lut_frac_level(const CircuitPortId& circuit_port_id)
return port_lut_frac_level_[circuit_port_id];
}
/* Return if the port drives or is driven by a harden logic inside a LUT */
bool CircuitLibrary::port_is_harden_lut_port(const CircuitPortId& circuit_port_id) const {
/* validate the circuit_port_id */
VTR_ASSERT(valid_circuit_port_id(circuit_port_id));
return port_is_harden_lut_port_[circuit_port_id];
}
/* Return indices of internal nodes in a LUT multiplexing structure to which the output port is wired to */
std::vector<size_t> CircuitLibrary::port_lut_output_mask(const CircuitPortId& circuit_port_id) const {
/* validate the circuit_port_id */
@ -1390,6 +1397,7 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id,
port_inv_model_ids_.push_back(CircuitModelId::INVALID());
port_tri_state_maps_.emplace_back();
port_lut_frac_level_.push_back(-1);
port_is_harden_lut_port_.push_back(false);
port_lut_output_masks_.emplace_back();
port_sram_orgz_.push_back(NUM_CONFIG_PROTOCOL_TYPES);
@ -1576,6 +1584,17 @@ void CircuitLibrary::set_port_lut_frac_level(const CircuitPortId& circuit_port_i
return;
}
/* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */
void CircuitLibrary::set_port_is_harden_lut_port(const CircuitPortId& circuit_port_id,
const bool& is_harden_lut_port) {
/* validate the circuit_port_id */
VTR_ASSERT(valid_circuit_port_id(circuit_port_id));
/* Make sure this is a LUT */
VTR_ASSERT(CIRCUIT_MODEL_LUT == model_type(port_model_ids_[circuit_port_id]));
port_is_harden_lut_port_[circuit_port_id] = is_harden_lut_port;
return;
}
/* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */
void CircuitLibrary::set_port_lut_output_mask(const CircuitPortId& circuit_port_id,
const std::vector<size_t>& lut_output_masks) {

4
libopenfpga/libarchopenfpga/src/circuit_library.h
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@ -289,6 +289,7 @@ class CircuitLibrary {
bool port_is_config_enable(const CircuitPortId& circuit_port_id) const;
bool port_is_prog(const CircuitPortId& circuit_port_id) const;
size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const;
bool port_is_harden_lut_port(const CircuitPortId& circuit_port_id) const;
std::vector<size_t> port_lut_output_mask(const CircuitPortId& circuit_port_id) const;
std::string port_tri_state_map(const CircuitPortId& circuit_port_id) const;
CircuitModelId port_tri_state_model(const CircuitPortId& circuit_port_id) const;
@ -383,6 +384,8 @@ class CircuitLibrary {
const std::string& tri_state_map);
void set_port_lut_frac_level(const CircuitPortId& circuit_port_id,
const size_t& lut_frac_level);
void set_port_is_harden_lut_port(const CircuitPortId& circuit_port_id,
const bool& is_harden_lut_port);
void set_port_lut_output_mask(const CircuitPortId& circuit_port_id,
const std::vector<size_t>& lut_output_masks);
void set_port_sram_orgz(const CircuitPortId& circuit_port_id,
@ -563,6 +566,7 @@ class CircuitLibrary {
vtr::vector<CircuitPortId, CircuitModelId> port_inv_model_ids_;
vtr::vector<CircuitPortId, std::string> port_tri_state_maps_;
vtr::vector<CircuitPortId, size_t> port_lut_frac_level_;
vtr::vector<CircuitPortId, bool> port_is_harden_lut_port_;
vtr::vector<CircuitPortId, std::vector<size_t>> port_lut_output_masks_;
vtr::vector<CircuitPortId, enum e_config_protocol_type> port_sram_orgz_;

10
libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
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@ -454,6 +454,16 @@ void read_xml_circuit_port(pugi::xml_node& xml_port,
circuit_lib.set_port_lut_frac_level(port, get_attribute(xml_port, "lut_frac_level", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1));
}
/* Identify if the port carries a harden functionality rather than a reconfigurable port
* This is only applicable to LUT circuit models.
* The super LUT circuit model (whose netlists are supposed to be provided by users) contains
* some hard logic inside, e.g., a carry logic.
* By default, a port does NOT carry a hard functionality
*/
if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) {
circuit_lib.set_port_is_harden_lut_port(port, get_attribute(xml_port, "is_harden_lut_port", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
}
/* Identify the output mask of the port in LUTs, by default it will be applied to each pin of this port
* This is only applicable to output ports of a LUT
*/

8
libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
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@ -186,6 +186,14 @@ void write_xml_circuit_port(std::fstream& fp,
}
}
/* LUT harden port attributes */
if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) {
if (true == circuit_lib.port_is_harden_lut_port(port)) {
write_xml_attribute(fp, "is_harden_lut_port", "true");
}
}
/* I/O port attributes */
if (true == circuit_lib.port_is_io(port)) {
write_xml_attribute(fp, "is_io", "true");