From b2984b46eeefc61e0bb582d80c41c83e4dd48f3b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Feb 2021 21:15:57 -0700 Subject: [PATCH] [Tool] Upgrade libopenfpga to support superLUT-related XML syntax --- .../libarchopenfpga/src/circuit_library.cpp | 19 +++++++++++++++++++ .../libarchopenfpga/src/circuit_library.h | 4 ++++ .../src/read_xml_circuit_library.cpp | 10 ++++++++++ .../src/write_xml_circuit_library.cpp | 8 ++++++++ 4 files changed, 41 insertions(+) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index f63cbcfd3..f56b94199 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -964,6 +964,13 @@ size_t CircuitLibrary::port_lut_frac_level(const CircuitPortId& circuit_port_id) return port_lut_frac_level_[circuit_port_id]; } +/* Return if the port drives or is driven by a harden logic inside a LUT */ +bool CircuitLibrary::port_is_harden_lut_port(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_harden_lut_port_[circuit_port_id]; +} + /* Return indices of internal nodes in a LUT multiplexing structure to which the output port is wired to */ std::vector CircuitLibrary::port_lut_output_mask(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ @@ -1390,6 +1397,7 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, port_inv_model_ids_.push_back(CircuitModelId::INVALID()); port_tri_state_maps_.emplace_back(); port_lut_frac_level_.push_back(-1); + port_is_harden_lut_port_.push_back(false); port_lut_output_masks_.emplace_back(); port_sram_orgz_.push_back(NUM_CONFIG_PROTOCOL_TYPES); @@ -1576,6 +1584,17 @@ void CircuitLibrary::set_port_lut_frac_level(const CircuitPortId& circuit_port_i return; } +/* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ +void CircuitLibrary::set_port_is_harden_lut_port(const CircuitPortId& circuit_port_id, + const bool& is_harden_lut_port) { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + /* Make sure this is a LUT */ + VTR_ASSERT(CIRCUIT_MODEL_LUT == model_type(port_model_ids_[circuit_port_id])); + port_is_harden_lut_port_[circuit_port_id] = is_harden_lut_port; + return; +} + /* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ void CircuitLibrary::set_port_lut_output_mask(const CircuitPortId& circuit_port_id, const std::vector& lut_output_masks) { diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index 415d1d4be..d2feee52b 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -289,6 +289,7 @@ class CircuitLibrary { bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; + bool port_is_harden_lut_port(const CircuitPortId& circuit_port_id) const; std::vector port_lut_output_mask(const CircuitPortId& circuit_port_id) const; std::string port_tri_state_map(const CircuitPortId& circuit_port_id) const; CircuitModelId port_tri_state_model(const CircuitPortId& circuit_port_id) const; @@ -383,6 +384,8 @@ class CircuitLibrary { const std::string& tri_state_map); void set_port_lut_frac_level(const CircuitPortId& circuit_port_id, const size_t& lut_frac_level); + void set_port_is_harden_lut_port(const CircuitPortId& circuit_port_id, + const bool& is_harden_lut_port); void set_port_lut_output_mask(const CircuitPortId& circuit_port_id, const std::vector& lut_output_masks); void set_port_sram_orgz(const CircuitPortId& circuit_port_id, @@ -563,6 +566,7 @@ class CircuitLibrary { vtr::vector port_inv_model_ids_; vtr::vector port_tri_state_maps_; vtr::vector port_lut_frac_level_; + vtr::vector port_is_harden_lut_port_; vtr::vector> port_lut_output_masks_; vtr::vector port_sram_orgz_; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index c574e890e..4fc3ddbb4 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -454,6 +454,16 @@ void read_xml_circuit_port(pugi::xml_node& xml_port, circuit_lib.set_port_lut_frac_level(port, get_attribute(xml_port, "lut_frac_level", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1)); } + /* Identify if the port carries a harden functionality rather than a reconfigurable port + * This is only applicable to LUT circuit models. + * The super LUT circuit model (whose netlists are supposed to be provided by users) contains + * some hard logic inside, e.g., a carry logic. + * By default, a port does NOT carry a hard functionality + */ + if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) { + circuit_lib.set_port_is_harden_lut_port(port, get_attribute(xml_port, "is_harden_lut_port", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + } + /* Identify the output mask of the port in LUTs, by default it will be applied to each pin of this port * This is only applicable to output ports of a LUT */ diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp index 954f9044f..f96780a92 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -186,6 +186,14 @@ void write_xml_circuit_port(std::fstream& fp, } } + /* LUT harden port attributes */ + if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) { + if (true == circuit_lib.port_is_harden_lut_port(port)) { + write_xml_attribute(fp, "is_harden_lut_port", "true"); + } + } + + /* I/O port attributes */ if (true == circuit_lib.port_is_io(port)) { write_xml_attribute(fp, "is_io", "true");