Merge pull request #236 from lnis-uofu/tpagarani_dev

Tpagarani dev

openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga

@@ -10,7 +10,8 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+#link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+link_openfpga_arch  --sort_gsb_chan_node_in_edges
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

openfpga_flow/scripts/run_fpga_flow.py

@@ -261,6 +261,8 @@ def main():
             run_ace2()
             run_pro_blif_3arg()
             run_rewrite_verilog()
+        else: 
+            shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif")
     if (args.fpga_flow == "vpr_blif"):
         collect_files_for_vpr()
     logger.info("Runing OpenFPGA Shell Engine ")

openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf

@@ -9,7 +9,7 @@
 [GENERAL]
 run_engine=openfpga_shell
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
+power_analysis = false
 spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
@@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml