From 3a587f663a838589dda9c1a2e64d3852ff56e751 Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Mon, 15 Feb 2021 02:36:02 -0800 Subject: [PATCH 1/2] copy yosys output file in case power analysis setting is off --- openfpga_flow/scripts/run_fpga_flow.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index ca7788653..26116f0ec 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -261,6 +261,8 @@ def main(): run_ace2() run_pro_blif_3arg() run_rewrite_verilog() + else: + shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif") if (args.fpga_flow == "vpr_blif"): collect_files_for_vpr() logger.info("Runing OpenFPGA Shell Engine ") From 426b6449d87915bfe115f7236d1a7cb355843da3 Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Mon, 15 Feb 2021 02:45:38 -0800 Subject: [PATCH 2/2] change the test to turn off power analysis --- .../quicklogic_flow_example_script.openfpga | 3 ++- .../tasks/quicklogic_tests/flow_test/config/task.conf | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga index 5adab1c51..8c0246871 100644 --- a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga @@ -10,7 +10,8 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +#link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 67d074bd0..2c2848e05 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 20*60 @@ -18,7 +18,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml