tangxifan
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66047e4a45
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refactoring Verilog simulation flag generations
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2019-11-05 13:45:11 -07:00 |
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tangxifan
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13f2d33d37
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refactored fpga_define.v generation
Please enter the commit message for your changes. Lines starting
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2019-11-05 12:41:43 -07:00 |
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tangxifan
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8ef9e994d8
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rename source files to be what they are actually doing
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2019-11-05 12:18:23 -07:00 |
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tangxifan
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aaaf7a0d19
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remove legacy codes in writing include netlists
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2019-11-04 21:06:14 -07:00 |
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tangxifan
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ebab0e91ef
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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tangxifan
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69bc858e62
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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tangxifan
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1fb29df1e2
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cleaning verilog file lines
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2019-11-03 17:58:18 -07:00 |
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tangxifan
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0ec465d4e1
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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tangxifan
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c681726124
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try to enlarge write buffers in ini writer, but these codes should be fully reworked
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2019-11-02 18:33:05 -06:00 |
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tangxifan
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3ad2a93539
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start bring back ini writer bit by bit
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2019-11-02 18:20:25 -06:00 |
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tangxifan
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cb74d120e7
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shadow ini writer to help debugging
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2019-11-02 17:31:05 -06:00 |
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tangxifan
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fc164abd49
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remove unused variable in sim info writer
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2019-11-02 16:35:32 -06:00 |
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tangxifan
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e1a7a2895a
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simulation ini file name can be customizable
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2019-11-02 09:59:34 -06:00 |
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tangxifan
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d5d7450ce7
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make simulation ini writing as an option
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2019-11-02 09:46:12 -06:00 |
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tangxifan
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c3db880599
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adding explicit file path to simulation info writer
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2019-11-02 09:21:02 -06:00 |
Ganesh Gore
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a0512e40b1
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Created intermidiate file for modelsim simulation
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2019-11-01 18:20:00 -06:00 |
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tangxifan
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55fbd72293
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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tangxifan
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4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
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7c116aac2f
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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tangxifan
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fe005f1f56
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remove legacy codes for Verilog formal verification testbench generation
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2019-10-28 15:21:14 -06:00 |
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tangxifan
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c047fd3cb2
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plugged in the refactored formal verification Verilog testbench using random vectors
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2019-10-28 15:10:29 -06:00 |
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tangxifan
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ccabe4ce2a
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refactoring Verilog formal verification top testbench using random vectors
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2019-10-28 14:45:51 -06:00 |
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tangxifan
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fb2f003d5b
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add top module generation and refactored verilog generation for top module
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2019-10-23 12:16:58 -06:00 |
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tangxifan
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dafab3907e
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refactored routing module generation and verilog writing
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2019-10-23 11:46:55 -06:00 |
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tangxifan
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89c8d089a3
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add grid module generation
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2019-10-22 16:14:11 -06:00 |
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tangxifan
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520e145af2
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move mux_lib to fpga_x2p_setup
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2019-10-19 19:13:52 -06:00 |
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tangxifan
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04f0fbebf7
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plug in module graph to feed verilog writers
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2019-10-18 21:59:22 -06:00 |
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tangxifan
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190449c06f
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refactoring top-level module with clb2clb direct connection
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2019-10-17 17:29:04 -06:00 |
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tangxifan
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4b56b755f2
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refactored instanciation of routing modules in top module
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2019-10-14 21:06:10 -06:00 |
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tangxifan
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bd6a0c6a55
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refactored grid instance addition to top module
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2019-10-14 17:47:10 -06:00 |
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tangxifan
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f779ad7ecf
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bug fixing for global and gpio port wiring; start refactoring top-level module
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2019-10-14 15:53:04 -06:00 |
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tangxifan
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997bfdbb95
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move the refactored function for physical block Verilog generation to a new source file
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2019-10-07 16:03:15 -06:00 |
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tangxifan
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3ca6f08aa4
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start refactoring physical block Verilog generation
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2019-10-06 19:27:55 -06:00 |
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tangxifan
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d7ac7d3649
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start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
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tangxifan
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d83cad7c2e
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refactoring Verilog generation for routing channels
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2019-09-16 17:35:51 -06:00 |
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tangxifan
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f69ce708ca
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rework on the order of top-level functions
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2019-09-13 21:59:52 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
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63f40f48fa
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-24 19:23:33 -06:00 |
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tangxifan
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27b619554d
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add stats for verilog modules
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2019-08-23 20:23:42 -06:00 |
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tangxifan
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ad06e9c98c
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plug in module manager
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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fcb31e4c24
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add stats for verilog modules
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2019-08-23 18:41:16 -06:00 |
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tangxifan
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8eebca9daa
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plug in module manager
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2019-08-23 17:39:29 -06:00 |
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tangxifan
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aa7f3bef7f
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fixed bugs in configure pb_rr_graph and dependence on testbenches
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2019-08-16 18:20:30 -06:00 |
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tangxifan
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d2d8af5416
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bug fixing for pb_type num_conf_bits and num_iopads stats
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2019-08-13 17:34:09 -06:00 |
Baudouin Chauviere
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8f5ad2eb67
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Snapshot of progress
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2019-07-02 10:10:48 -06:00 |
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Baudouin Chauviere
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7c742f1cbb
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Stable, is_explicit propagated through the code. Not implemented though except for muxes
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2019-06-27 10:29:57 -06:00 |
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Baudouin Chauviere
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0ce9846e47
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Stable, unfinished
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2019-06-26 16:54:41 -06:00 |
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Baudouin Chauviere
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87ddca9f57
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commiting current work. Stable but function not implemented yet
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2019-06-26 14:22:02 -06:00 |
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tangxifan
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c879e7f6c5
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fixed a critical bug when instanciating Connection blocks
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2019-06-26 11:33:02 -06:00 |