tangxifan
|
314e458632
|
[Test] Update task configuration to use post-yosys .v file in verification
|
2021-01-13 15:42:45 -07:00 |
|
tangxifan
|
c5a2027f36
|
[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
|
2021-01-13 15:41:48 -07:00 |
|
tangxifan
|
7af6d7f07d
|
[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
|
2021-01-13 15:38:44 -07:00 |
|
tangxifan
|
91f12071d5
|
[Test] Use counter4bit in the multi-clock test
|
2021-01-13 13:34:59 -07:00 |
|
tangxifan
|
ccf3e037ff
|
[Benchmark] Change multi-clock counter from 8-bit to 4-bit
|
2021-01-13 13:31:06 -07:00 |
|
tangxifan
|
250adb01cf
|
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
|
2021-01-13 13:18:31 -07:00 |
|
tangxifan
|
99e2a068fb
|
[Test] Add a test case for multi-clock
|
2021-01-12 18:06:25 -07:00 |
|
tangxifan
|
2f1aceda67
|
[Doc] Update documentation about architecture naming rules
|
2021-01-12 18:01:24 -07:00 |
|
tangxifan
|
9fa49c401c
|
[Arch] Add openfpga architecture which uses 4 global clocks
|
2021-01-12 18:00:22 -07:00 |
|
tangxifan
|
16b4e89326
|
[Doc] Update documentation for VPR architectures
|
2021-01-12 17:57:40 -07:00 |
|
tangxifan
|
7ccdff4543
|
[Arch] Add an architecture using 4 clocks
|
2021-01-12 17:55:57 -07:00 |
|
tangxifan
|
3790f2c26a
|
[Benchmark] Add 2-clock micro benchmark
|
2021-01-12 17:48:52 -07:00 |
|
tangxifan
|
a0b9f2b40d
|
Merge pull request #170 from lnis-uofu/dev
Extended Support on Defining Global Ports from Physical Tile Ports
|
2021-01-11 10:02:31 -07:00 |
|
tangxifan
|
e58e1e86c2
|
[Test] Update test case to use new shell script
|
2021-01-10 11:09:10 -07:00 |
|
tangxifan
|
18d2a8ce19
|
[Flow] Add new script for fixed device layout using global tile clock
|
2021-01-10 11:08:02 -07:00 |
|
tangxifan
|
aaf582acc5
|
[Arch] Bug fix
|
2021-01-10 11:05:57 -07:00 |
|
tangxifan
|
1c68e43acf
|
[Test] Add new test case for registerable I/O architecture
|
2021-01-10 11:00:21 -07:00 |
|
tangxifan
|
f21d22f691
|
[Doc] Update README for new architectures
|
2021-01-10 10:54:59 -07:00 |
|
tangxifan
|
dfb3e32147
|
[Arch] Add openfpga archiecture for registerable I/O
|
2021-01-10 10:54:41 -07:00 |
|
tangxifan
|
853e7b1a40
|
[Arch] Add vpr architecture where I/O can be either combinational or registered
|
2021-01-10 10:54:09 -07:00 |
|
tangxifan
|
43418cd76b
|
[Test] Deploy pipeplined and2 to test cases
|
2021-01-10 10:28:22 -07:00 |
|
tangxifan
|
6521aa2e7a
|
[Benchmark] Bug fix in pipelined and2 benchmark
|
2021-01-10 10:27:59 -07:00 |
|
tangxifan
|
4412bbd084
|
[Benchmark] Add a micro benchmark to test pipelined architecture
|
2021-01-10 10:21:30 -07:00 |
|
tangxifan
|
0b74575606
|
[Arch] Update arch using global reset tile port
|
2021-01-09 18:04:55 -07:00 |
|
tangxifan
|
7b24da267a
|
[Arch] Remove port size XML syntax
|
2021-01-09 16:30:46 -07:00 |
|
tangxifan
|
9f12b25a24
|
[Arch] Add port size to global port defined thru tile annotation
|
2021-01-09 16:23:28 -07:00 |
|
tangxifan
|
0f5f0a3527
|
[Arch] Add x,y coordinates to global port definition
|
2021-01-09 15:50:09 -07:00 |
|
tangxifan
|
a14a56772a
|
[Arch] Introduce new XML syntax for global port in tile annotation
|
2021-01-09 15:48:42 -07:00 |
Lalit Sharma
|
8a5741b1ae
|
Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow
|
2021-01-08 07:08:24 -08:00 |
|
tangxifan
|
a813c9016b
|
[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
|
2021-01-04 17:39:13 -07:00 |
|
tangxifan
|
06af30ef10
|
[Test] Add test case for the SCFF usage in configuration chain
|
2021-01-04 17:30:19 -07:00 |
|
tangxifan
|
709ee1b842
|
[HDL] Update dff netlist for SCFF used in configuration chain
|
2021-01-04 17:17:35 -07:00 |
|
tangxifan
|
c97a92d628
|
[Arch] Patch openfpga architecture for ccff circuit model port requirement
|
2021-01-04 17:15:50 -07:00 |
|
tangxifan
|
294ad97d38
|
[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
|
2021-01-04 14:56:49 -07:00 |
|
tangxifan
|
722a9bcf63
|
[HDL] Add scan-chain DFF cell with configuration enable signal
|
2021-01-04 14:31:26 -07:00 |
|
Lalit Sharma
|
2484721a45
|
Updating write_verilog_testbench by removing option explicit_port_mapping
|
2020-12-22 22:17:50 -08:00 |
|
Lalit Sharma
|
3c9e4919b4
|
Updating variable name in ys to call BLIF output file.
|
2020-12-18 03:18:46 -08:00 |
|
Lalit Sharma
|
1f994319fd
|
Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
|
2020-12-16 04:19:56 -08:00 |
|
Lalit Sharma
|
891e2f8aa3
|
Adding arch xml from SOFA repo. Also updating the script with its file location
|
2020-12-16 04:14:18 -08:00 |
|
Lalit Sharma
|
0ee3efb306
|
Adding a testcase to run yosys quicklogic flow
|
2020-12-10 02:41:43 -08:00 |
|
tangxifan
|
6b50bbf986
|
Merge pull request #134 from lnis-uofu/ganesh_dev
Support Delay Customization in OpenFPGA Task Configuration File
|
2020-12-08 15:32:48 -07:00 |
|
tangxifan
|
6001da3a40
|
[Arch] Bug fix in tileable I/O arch example
|
2020-12-04 17:56:54 -07:00 |
|
tangxifan
|
1d0bdcfeca
|
[Arch] Simplify the grid layout modeling
|
2020-12-04 17:38:44 -07:00 |
|
tangxifan
|
1c3f625e41
|
[Arch] Force empty tiles at corners for tileable I/O arch example
|
2020-12-04 17:11:06 -07:00 |
|
tangxifan
|
0cb8457e21
|
[Test] Add test case for tileable I/O
|
2020-12-04 16:02:47 -07:00 |
|
tangxifan
|
186eb0f0a4
|
[Arch] Add tileable I/O architecture example
|
2020-12-04 15:59:39 -07:00 |
ganeshgore
|
289d9d2169
|
[Bugfix] Honors yosys_tmpl parameter in flow script
|
2020-12-03 12:24:24 -07:00 |
|
tangxifan
|
412fb5bb31
|
[Arch] Bug fix due to valid default value parser
|
2020-12-02 17:51:50 -07:00 |
|
tangxifan
|
179b0ce304
|
[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
|
2020-11-30 18:11:47 -07:00 |
|
tangxifan
|
c7604ab94f
|
[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
|
2020-11-30 18:02:00 -07:00 |
|
tangxifan
|
ff53d2c375
|
[HDL] Add new Scan-chain DFF cell
|
2020-11-30 17:54:10 -07:00 |
|
tangxifan
|
ad703ad85b
|
[HDL] Add new gpio cell with protection circuitry
|
2020-11-30 17:52:39 -07:00 |
|
tangxifan
|
27a480b5f8
|
[Test] arch name fix in the test case
|
2020-11-30 17:45:54 -07:00 |
|
tangxifan
|
7a0a3398d4
|
[Arch] Add new architecture to test global reset ports defined thru tile ports
|
2020-11-30 17:43:41 -07:00 |
|
tangxifan
|
a1d3b439d3
|
[Test] Add a new test case to define a global reset port from a global tile port
|
2020-11-30 17:19:12 -07:00 |
|
tangxifan
|
a60bd4d14a
|
[Arch] Bug fix in nature fracturable architecture
|
2020-11-25 22:48:26 -07:00 |
|
ganeshgore
|
7db030018c
|
[Bug] Fixed variable file location
|
2020-11-25 22:44:40 -07:00 |
|
tangxifan
|
b8559249dc
|
[Test] Bug fix in task configuration file
|
2020-11-25 22:23:27 -07:00 |
|
tangxifan
|
26e4db56ad
|
[Test] Add new test case for the native fracturable LUT4
|
2020-11-25 22:21:23 -07:00 |
|
tangxifan
|
17070c6405
|
[Doc] Update README in openfpga arch directory for native fracturable LUT design
|
2020-11-25 22:19:20 -07:00 |
|
tangxifan
|
f6a667de58
|
[Arch] Add openfpga architecture using native fracturable LUT
|
2020-11-25 22:18:03 -07:00 |
|
tangxifan
|
eda671592e
|
[Doc] Update README about new keyword about fracturable LUT
|
2020-11-25 22:12:56 -07:00 |
|
tangxifan
|
0f841aa6d1
|
[Arch] Add an example architecture using native fracturable LUT
|
2020-11-25 22:11:14 -07:00 |
|
ganeshgore
|
59bd7d0f18
|
[Flow] Changed substitute to safe_sustitute option
|
2020-11-25 22:09:36 -07:00 |
|
ganeshgore
|
fefba0db59
|
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
|
2020-11-25 17:29:53 -07:00 |
|
ganeshgore
|
1d993296d8
|
[Flow] Example of using test variable in task conf
|
2020-11-25 17:25:12 -07:00 |
|
ganeshgore
|
1554f583b7
|
[Flow] Now support explicit variable file for task
|
2020-11-25 17:22:41 -07:00 |
|
tangxifan
|
fd80cacaa3
|
[Flow] Add example script for behaviorial verilog generation
|
2020-11-22 21:14:10 -07:00 |
|
tangxifan
|
617f7e3062
|
[Flow] disable signal initialization for behavioral verilog generation
|
2020-11-22 21:13:22 -07:00 |
|
tangxifan
|
5eb04e6fff
|
[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
|
2020-11-22 20:53:32 -07:00 |
|
tangxifan
|
655da9f3d0
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
tangxifan
|
348872f8a4
|
[Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes
|
2020-11-22 16:12:28 -07:00 |
|
tangxifan
|
845436fa71
|
[Test] Add sequential benchmark for global tile clock test case
|
2020-11-17 14:34:54 -07:00 |
|
tangxifan
|
91b0dbbaa2
|
[Script] Add example openfpga shell run script when using global tile clocks
|
2020-11-17 14:33:12 -07:00 |
|
tangxifan
|
485258a9ea
|
[Test] Add test case for global clock from tiles
|
2020-11-10 19:24:25 -07:00 |
|
tangxifan
|
f29916921a
|
[Arch] Add openfpga arch for using global clocks from tiles
|
2020-11-10 19:20:08 -07:00 |
|
tangxifan
|
a6531d9e8d
|
[Arch] Add k4 arch using global clock from tile port (with zero fc)
|
2020-11-10 19:17:34 -07:00 |
|
tangxifan
|
75ce4b5e25
|
[Arch] Fine tune example arch
|
2020-11-10 14:38:47 -07:00 |
|
tangxifan
|
d127304760
|
[Arch] Update sample arch using local clock from physical tile ports
|
2020-11-10 14:31:58 -07:00 |
|
tangxifan
|
4ca2a129c2
|
[Arch] Add an sample architecture where global clock port is defined from tile ports
|
2020-11-10 11:47:03 -07:00 |
|
tangxifan
|
70734abc35
|
[Arch] Remove QN from stdcell arch
|
2020-11-06 11:20:13 -07:00 |
|
tangxifan
|
1a79a55646
|
[HDL] Add DFF cell with reset but only 1 output
|
2020-11-06 11:19:19 -07:00 |
|
tangxifan
|
2aab8bf910
|
[Arch] Use single-output DFF for a standard cell FPGA
|
2020-11-06 10:26:39 -07:00 |
|
tangxifan
|
7d46b35296
|
[HDL] Add single-output DFF HDL
|
2020-11-06 10:18:37 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
55f7a2c187
|
Merge pull request #116 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
|
2020-11-04 21:55:37 -07:00 |
|
tangxifan
|
bce8233019
|
[Arch] Bug fix in caravel arch
|
2020-11-04 20:58:58 -07:00 |
|
tangxifan
|
6b48ee7f0b
|
[Test] Add new test for caravel io support
|
2020-11-04 20:58:40 -07:00 |
|
tangxifan
|
c85edb4738
|
[Arch] Bug fix for embedded io arch
|
2020-11-04 20:52:47 -07:00 |
|
tangxifan
|
a6c7bb2c48
|
[Arch] Update OpenFPGA arch for new syntax on I/O
|
2020-11-04 20:24:02 -07:00 |
|
tangxifan
|
dd86f7f464
|
[Arch] Path architecture for caravel i/o interface
|
2020-11-04 17:16:21 -07:00 |
|
tangxifan
|
c074e88dcd
|
[HDL] Add embedded I/O HDL for Caravel SoC interface
|
2020-11-04 17:09:59 -07:00 |
|
tangxifan
|
aebf7453d0
|
[Arch] Add architecture files with compatible I/O capacity with caravel SoC
|
2020-11-04 16:57:00 -07:00 |
|
tangxifan
|
61376a2979
|
[Test] Add test cases for various tile organization
|
2020-11-04 16:32:52 -07:00 |
|
tangxifan
|
cf455df555
|
[Arch] Add architecture for bottom-right and top-left tile organization
|
2020-11-04 16:24:36 -07:00 |
|
tangxifan
|
46ca406f10
|
[Arch] Add a new vpr architecture with new tile organization
|
2020-11-04 16:20:01 -07:00 |
|
tangxifan
|
049ca14461
|
[Doc] Add new naming rules for vpr architecture files
|
2020-11-04 16:17:56 -07:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
5d41cc6d23
|
Merge pull request #114 from LNIS-Projects/dev
Support I/O interfaces for Embedded FPGAs
|
2020-11-02 21:10:52 -07:00 |
|
tangxifan
|
c036c87d6d
|
[HDL] Bug fix in the GP output pad
|
2020-11-02 18:37:53 -07:00 |
|
tangxifan
|
3b49e6d090
|
[Arch] Patch embedded IO architecture by forcing only 1 pad per block
|
2020-11-02 15:39:31 -07:00 |
|
tangxifan
|
c512644a09
|
[Arch] Patch embedded I/O example architecture
|
2020-11-02 15:16:19 -07:00 |