AurelienUoU
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64a67dceaf
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Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation
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2019-07-18 16:34:47 -06:00 |
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AurelienUoU
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f4e999ef6d
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Correct error in demo, set a new generated ff_${benchmark}.v file rather than overwrite
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2019-07-18 16:33:23 -06:00 |
tangxifan
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6e1d49d74e
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start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
Baudouin Chauviere
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65122d04b3
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 13:37:21 -06:00 |
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AurelienUoU
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509c1d2c80
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Link path correction
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2019-07-16 13:13:58 -06:00 |
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Baudouin Chauviere
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69014704ef
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Explicit verilog final push
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2019-07-16 13:13:30 -06:00 |
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AurelienUoU
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3d079c9421
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Add folder creation in tuto_fpga_flow.sh to ease the use
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2019-07-16 07:20:21 -06:00 |
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AurelienUoU
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b810b5cab9
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fpga_flow bug fix + upload k8 architecture
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2019-07-16 07:04:45 -06:00 |
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AurelienUoU
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35e1962732
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Merge branch 'dev' into documentation
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2019-07-15 21:19:26 -06:00 |
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AurelienUoU
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19ccbce9d0
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Rename option to use circuit_model rather than spice_model
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2019-07-12 16:18:28 -06:00 |
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AurelienUoU
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e65cf9f5fd
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Update ERI-demo
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2019-07-12 08:55:19 -06:00 |
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tangxifan
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e633e3d17b
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update fpga_flow scripts to support vpr_only flow
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2019-07-11 19:40:58 -06:00 |
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tangxifan
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9c203ca4d2
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bug fixing in SDC generator
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2019-07-11 17:10:08 -06:00 |
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AurelienUoU
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1848771e54
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Add explicit mapping option into fpga_flow
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2019-07-11 14:44:30 -06:00 |
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AurelienUoU
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ad0b4b3acd
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Merge remote-tracking branch 'origin/dev' into documentation
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2019-07-11 10:15:26 -06:00 |
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tangxifan
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31749fe62b
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fix bugs in fpga_flow.pl
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2019-07-10 21:12:00 -06:00 |
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AurelienUoU
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9d7ae2f6ec
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Update tutorial flow demo draft 6
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2019-07-10 15:42:31 -06:00 |
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tangxifan
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acee0161c7
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Merge branch 'tileable_routing' into dev
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2019-07-10 15:13:24 -06:00 |
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tangxifan
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206fc84a0e
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minor fix in fpga_flow
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2019-07-10 15:12:51 -06:00 |
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AurelienUoU
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a47711203c
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Tuto update draft 5
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2019-07-10 14:59:03 -06:00 |
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AurelienUoU
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905293820f
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Draft2
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2019-07-10 10:37:05 -06:00 |
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AurelienUoU
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20ce020eb6
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Tutorial rewrite draft 1
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2019-07-10 10:03:30 -06:00 |
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Baudouin Chauviere
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4ca0967453
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-09 14:35:51 -06:00 |
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Baudouin Chauviere
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792ba23f4f
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Correction pre-merge
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2019-07-09 14:34:34 -06:00 |
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Baudouin Chauviere
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589f58b55e
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Regression test succeeded
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2019-07-09 09:18:06 -06:00 |
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AurelienUoU
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8366f9e7b7
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Update tutorial
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2019-07-08 16:18:08 -06:00 |
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AurelienUoU
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b4a78abc04
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Update doc
Merge remote-tracking branch 'origin/heterogeneous' into dev
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2019-07-05 12:25:37 -06:00 |
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tangxifan
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c8ceb8f7d5
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update fpga_flow.pl
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2019-07-04 12:23:11 -06:00 |
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tangxifan
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5a50fa84d1
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keep updating fpga_flow.pl to use system call
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2019-07-03 22:57:43 -06:00 |
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tangxifan
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6b894640c7
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bug fixing in fpga_flow.pl
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2019-07-03 14:59:05 -06:00 |
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tangxifan
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d5137eb424
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-03 14:31:18 -06:00 |
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tangxifan
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5195faab8b
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Merge branch 'dev' into tileable_routing
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2019-07-03 14:30:39 -06:00 |
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tangxifan
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4f3cb0bdf3
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added tileable routing chanW adaption to fixed W router
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2019-07-03 14:29:50 -06:00 |
Ganesh Gore
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443a73954f
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Removed all local files
+ Removed local configurations and scripts from previous commit
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2019-07-03 14:26:06 -06:00 |
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tangxifan
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c9743e84da
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-03 14:12:47 -06:00 |
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tangxifan
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a539c6a2a7
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bug fixing in fpga_flow.pl
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2019-07-03 14:11:14 -06:00 |
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Ganesh Gore
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57ad71438b
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Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
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2019-07-03 13:39:52 -06:00 |
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AurelienUoU
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e13c703709
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Upload recent commit
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-07-03 13:09:34 -06:00 |
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AurelienUoU
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43e9d8afd1
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Add compact routing hierarchy option in fpga_flow
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2019-07-03 13:08:49 -06:00 |
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Ganesh Gore
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3c36a51011
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Added 'rewrite_path_in_file' back to repository
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2019-07-03 12:49:25 -06:00 |
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Ganesh Gore
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53486b8a89
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Added 'spice_simulator_path' in fpga_flow
added vpr_fpga_spice_simulator_path in fpga-flow script
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2019-07-03 12:30:56 -06:00 |
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tangxifan
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0c3e8bb70a
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add a new option to the router to enable conversion of route_chan_width to be tileable
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2019-07-03 12:11:48 -06:00 |
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tangxifan
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02398818a9
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update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
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2019-07-03 10:33:02 -06:00 |
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tangxifan
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4392c6bc3a
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bug fixing in fpga_flow scripts and add more print-out message for VPR
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2019-07-02 15:34:59 -06:00 |
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AurelienUoU
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60f7ab0465
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Start heterogeneous dev
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2019-07-02 10:16:10 -06:00 |
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Ganesh Gore
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54f6ca2687
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Added lattice benchmark settings
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2019-07-01 11:07:23 -06:00 |
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tangxifan
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c54f3905d5
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fixed broken fpga flow
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2019-06-28 13:07:04 -06:00 |
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tangxifan
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1332ba62e8
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update tileable rr_graph generator to improve routability and also enable assoicated testing
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2019-06-27 17:52:25 -06:00 |
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tangxifan
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4d3b5f12b4
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fixed bugs for UNIVERSAL and WILTON switch blocks
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2019-06-25 14:15:29 -06:00 |
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AurelienUoU
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c76dbaac33
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Update regression test avoiding overwritting files
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2019-06-14 11:44:44 -06:00 |