Added 'spice_simulator_path' in fpga_flow
added vpr_fpga_spice_simulator_path in fpga-flow script
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53486b8a89
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@ -168,6 +168,7 @@ sub print_usage()
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print " \t-vpr_fpga_spice_leakage_only : turn on leakage_only mode in VPR FPGA SPICE\n";
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print " \t-vpr_fpga_spice_parasitic_net_estimation_off : turn off parasitic_net_estimation in VPR FPGA SPICE\n";
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print " \t-vpr_fpga_spice_testbench_load_extraction_off : turn off testbench_load_extraction in VPR FPGA SPICE\n";
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print " \t-vpr_fpga_spice_simulator_path <string> : Specify simulator path\n";
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print " [ VPR - FPGA-Verilog Extension ] \n";
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print " \t-vpr_fpga_verilog : turn on Verilog Generator of VPR FPGA SPICE\n";
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print " \t-vpr_fpga_verilog_dir <verilog_path>: provide the path where generated verilog files will be written\n";
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@ -274,8 +275,7 @@ sub read_opt_into_hash($ $ $)
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sub opts_read()
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{
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# if no arguments detected, print the usage.
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if (-1 == $#ARGV)
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{
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if (-1 == $#ARGV) {
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print "Error : No input arguments!\n";
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print "Help desk:\n";
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&print_usage();
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@ -289,19 +289,15 @@ sub opts_read()
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my $argfd;
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# Check help fist
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$argfd = &spot_option($cur_arg,"-help");
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if (-1 != $argfd)
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{
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if (-1 != $argfd) {
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print "Help desk:\n";
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&print_usage();
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}
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# Then Check the debug with highest priority
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$argfd = &spot_option($cur_arg,"-debug");
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if (-1 != $argfd)
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{
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if (-1 != $argfd) {
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$opt_ptr->{"debug"} = "on";
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}
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else
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{
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} else {
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$opt_ptr->{"debug"} = "off";
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}
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# Check mandatory options
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@ -350,6 +346,7 @@ sub opts_read()
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&read_opt_into_hash("vpr_fpga_spice_leakage_only","off","off");
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&read_opt_into_hash("vpr_fpga_spice_parasitic_net_estimation_off","off","off");
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&read_opt_into_hash("vpr_fpga_spice_testbench_load_extraction_off","off","off");
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&read_opt_into_hash("vpr_fpga_spice_simulator_path","on","off");
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# FPGA-Verilog options
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# Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory"
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@ -1331,6 +1328,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
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if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) {
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$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}";
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}
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if ("on" eq $opt_ptr->{vpr_fpga_spice_simulator_path}) {
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$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_simulator_path $opt_ptr->{vpr_fpga_spice_simulator_path_val}";
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}
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if ("on" eq $opt_ptr->{vpr_fpga_spice_print_component_tb}) {
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$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_lut_testbench";
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$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_hardlogic_testbench";
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