Update doc

Merge remote-tracking branch 'origin/heterogeneous' into dev
2019-07-05 12:25:37 -06:00 · 2019-07-05 12:25:37 -06:00 · b4a78abc04
parent 3077efa74f 9e99048815
commit b4a78abc04
16 changed files with 1874 additions and 32 deletions
--- a/ERI_demo/ERI.sh
+++ b/ERI_demo/ERI.sh
@ -0,0 +1,49 @@
+#!/bin/bash
+# Regression test version 1.0
+
+# Set variables
+my_pwd=$PWD
+fpga_flow_scripts=${my_pwd}/fpga_flow/scripts
+vpr_path=${my_pwd}/vpr7_x2p/vpr
+benchmark="pipelined_8b_adder"
+include_netlists="_include_netlists.v"
+compiled_file="compiled_$benchmark"
+tb_formal_postfix="_top_formal_verification_random_tb"
+verilog_output_dirname="${vpr_path}${benchmark}_Verilog"
+log_file="${benchmark}_sim.log"
+new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh"
+template_sh="${PWD}/ERI_demo/eri_demo.sh"
+
+
+# Remove former log file
+rm -f $log_file
+rm -f $compiled_file
+
+# Rewite script
+cd $fpga_flow_scripts
+
+perl rewrite_path_in_file.pl -i $template_sh -o $new_reg_sh
+
+cd $my_pwd
+
+# Start the script -> run the fpga generation -> run the simulation -> check the log file
+source $new_reg_sh	# Leave us in vpr folder
+iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
+vvp $compiled_file -j 64 >> $log_file
+
+result=`grep "Succeed" $log_file`
+if ["$result" = ""]; then
+  result=`grep "Failed" $log_file`
+  if ["$result" = ""]; then
+    echo "Unexpected error, Verification didn't run"
+    cd $my_pwd
+    exit 1
+  else
+    echo "Verification failed"
+    cd $my_pwd
+    exit 2
+  fi
+else
+  echo "Verification succeed"
+  cd $my_pwd
+fi
--- a/ERI_demo/eri_demo.sh
+++ b/ERI_demo/eri_demo.sh
@ -0,0 +1,52 @@
+#!/bin/bash
+# Example of how to run vpr
+
+# Set variables
+# For FPGA-Verilog ONLY 
+benchmark="pipelined_8b_adder"
+OpenFPGA_path="OPENFPGAPATHKEYWORD"
+verilog_output_dirname="${benchmark}_Verilog"
+verilog_output_dirpath="$vpr_path"
+tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
+# VPR critical inputs
+template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml"
+arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml"
+blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif" 
+act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act "
+verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v"
+vpr_route_chan_width="300"
+fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
+ff_path="$vpr_path/VerilogNetlists/ff.v"
+new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
+ff_keyword="GENERATED_DIR_KEYWORD"
+ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
+arch_ff_keyword="FFPATHKEYWORD"
+tb_formal_ext="_formal_random_top_tb.v"
+formal_postfix="_top_formal_verification"
+clk_unmapped="clk\[0:0\]"
+clk_mapped="clk_fm"
+
+# Remove previous designs
+rm -rf $verilog_output_dirpath/$verilog_output_dirname
+
+mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
+
+#cd $fpga_flow_scripts
+perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
+perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
+
+# Move to vpr folder
+cd $vpr_path
+
+# Run VPR  
+./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --nodisp
+
+cd $fpga_flow_scripts
+perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
+
+rm $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext}
+perl rewrite_path_in_file.pl -i ${OpenFPGA_path}/ERI_demo/${benchmark}${tb_formal_ext} -o $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext}
+cd -
+
+sed -i 's/^clk\[0:0\]/clk_fm/' $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${formal_postfix}.v
+
--- a/ERI_demo/my_eri_demo.sh
+++ b/ERI_demo/my_eri_demo.sh
@ -0,0 +1,42 @@
+#!/bin/bash
+# Example of how to run vpr
+
+# Set variables
+# For FPGA-Verilog ONLY 
+benchmark="pipelined_32b_adder"
+OpenFPGA_path="/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA"
+verilog_output_dirname="${benchmark}_Verilog"
+verilog_output_dirpath="$vpr_path"
+tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
+# VPR critical inputs
+template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml"
+arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml"
+blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif" 
+act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act "
+verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v"
+vpr_route_chan_width="300"
+fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
+ff_path="$vpr_path/VerilogNetlists/ff.v"
+new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
+ff_keyword="GENERATED_DIR_KEYWORD"
+ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
+arch_ff_keyword="FFPATHKEYWORD"
+
+# Remove previous designs
+#rm -rf $verilog_output_dirpath/$verilog_output_dirname
+
+mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
+
+cd $fpga_flow_scripts
+perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
+perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
+
+# Move to vpr folder
+cd $vpr_path
+
+# Run VPR  
+./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator #--fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
+
+cd $fpga_flow_scripts
+perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
+cd -
--- a/ERI_demo/pipelined_8b_adder.act
+++ b/ERI_demo/pipelined_8b_adder.act
@ -0,0 +1,95 @@
+clk 0.5 0.2
+wen 0.5 0.2
+wen_st0 0.5 0.2
+wen_st1 0.5 0.2
+ren 0.5 0.2
+raddr[0] 0.5 0.2
+raddr[1] 0.5 0.2
+raddr[2] 0.5 0.2
+raddr[3] 0.5 0.2
+raddr[4] 0.5 0.2
+raddr[5] 0.5 0.2
+waddr[0] 0.5 0.2
+waddr[1] 0.5 0.2
+waddr[2] 0.5 0.2
+waddr[3] 0.5 0.2
+waddr[4] 0.5 0.2
+waddr[5] 0.5 0.2
+waddr_st0[0] 0.5 0.2
+waddr_st0[1] 0.5 0.2
+waddr_st0[2] 0.5 0.2
+waddr_st0[3] 0.5 0.2
+waddr_st0[4] 0.5 0.2
+waddr_st0[5] 0.5 0.2
+waddr_st1[0] 0.5 0.2
+waddr_st1[1] 0.5 0.2
+waddr_st1[2] 0.5 0.2
+waddr_st1[3] 0.5 0.2
+waddr_st1[4] 0.5 0.2
+waddr_st1[5] 0.5 0.2
+a[0] 0.5 0.2
+a[1] 0.5 0.2
+a[2] 0.5 0.2
+a[3] 0.5 0.2
+a[4] 0.5 0.2
+a[5] 0.5 0.2
+a[6] 0.5 0.2
+a_st0[0] 0.5 0.2
+a_st0[1] 0.5 0.2
+a_st0[2] 0.5 0.2
+a_st0[3] 0.5 0.2
+a_st0[4] 0.5 0.2
+a_st0[5] 0.5 0.2
+a_st0[6] 0.5 0.2
+a_st1[0] 0.5 0.2
+a_st1[1] 0.5 0.2
+a_st1[2] 0.5 0.2
+a_st1[3] 0.5 0.2
+a_st1[4] 0.5 0.2
+a_st1[5] 0.5 0.2
+a_st1[6] 0.5 0.2
+b[0] 0.5 0.2
+b[1] 0.5 0.2
+b[2] 0.5 0.2
+b[3] 0.5 0.2
+b[4] 0.5 0.2
+b[5] 0.5 0.2
+b[6] 0.5 0.2
+b_st0[0] 0.5 0.2
+b_st0[1] 0.5 0.2
+b_st0[2] 0.5 0.2
+b_st0[3] 0.5 0.2
+b_st0[4] 0.5 0.2
+b_st0[5] 0.5 0.2
+b_st0[6] 0.5 0.2
+b_st1[0] 0.5 0.2
+b_st1[1] 0.5 0.2
+b_st1[2] 0.5 0.2
+b_st1[3] 0.5 0.2
+b_st1[4] 0.5 0.2
+b_st1[5] 0.5 0.2
+b_st1[6] 0.5 0.2
+q[0] 0.5 0.2
+q[1] 0.5 0.2
+q[2] 0.5 0.2
+q[3] 0.5 0.2
+q[4] 0.5 0.2
+q[5] 0.5 0.2
+q[6] 0.5 0.2
+q[7] 0.5 0.2
+AplusB[0] 0.5 0.2
+AplusB[1] 0.5 0.2
+AplusB[2] 0.5 0.2
+AplusB[3] 0.5 0.2
+AplusB[4] 0.5 0.2
+AplusB[5] 0.5 0.2
+AplusB[6] 0.5 0.2
+AplusB[7] 0.5 0.2
+cint01 0.5 0.2
+cint02 0.5 0.2
+cint03 0.5 0.2
+cint04 0.5 0.2
+cint05 0.5 0.2
+cint06 0.5 0.2
+cint07 0.5 0.2
+zero00 0 0
--- a/ERI_demo/pipelined_8b_adder.blif
+++ b/ERI_demo/pipelined_8b_adder.blif
@ -0,0 +1,137 @@
+# Benchmark pipelined_32b_adder
+.model pipelined_32b_adder
+.inputs clk wen ren raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] a[0] a[1] a[2] a[3] a[4] a[5] a[6] b[0] b[1] b[2] b[3] b[4] b[5] b[6]
+.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7]
+
+# Start pipeline
+# Pipeline a
+.subckt shift D=a[0] clk=clk Q=a_st0[0]
+.subckt shift D=a_st0[0] clk=clk Q=a_st1[0]
+.subckt shift D=a[1] clk=clk Q=a_st0[1]
+.subckt shift D=a_st0[1] clk=clk Q=a_st1[1]
+.subckt shift D=a[2] clk=clk Q=a_st0[2]
+.subckt shift D=a_st0[2] clk=clk Q=a_st1[2]
+.subckt shift D=a[3] clk=clk Q=a_st0[3]
+.subckt shift D=a_st0[3] clk=clk Q=a_st1[3]
+.subckt shift D=a[4] clk=clk Q=a_st0[4]
+.subckt shift D=a_st0[4] clk=clk Q=a_st1[4]
+.subckt shift D=a[5] clk=clk Q=a_st0[5]
+.subckt shift D=a_st0[5] clk=clk Q=a_st1[5]
+.subckt shift D=a[6] clk=clk Q=a_st0[6]
+.subckt shift D=a_st0[6] clk=clk Q=a_st1[6]
+
+# Pipeline b
+.subckt shift D=b[0] clk=clk Q=b_st0[0]
+.subckt shift D=b_st0[0] clk=clk Q=b_st1[0]
+.subckt shift D=b[1] clk=clk Q=b_st0[1]
+.subckt shift D=b_st0[1] clk=clk Q=b_st1[1]
+.subckt shift D=b[2] clk=clk Q=b_st0[2]
+.subckt shift D=b_st0[2] clk=clk Q=b_st1[2]
+.subckt shift D=b[3] clk=clk Q=b_st0[3]
+.subckt shift D=b_st0[3] clk=clk Q=b_st1[3]
+.subckt shift D=b[4] clk=clk Q=b_st0[4]
+.subckt shift D=b_st0[4] clk=clk Q=b_st1[4]
+.subckt shift D=b[5] clk=clk Q=b_st0[5]
+.subckt shift D=b_st0[5] clk=clk Q=b_st1[5]
+.subckt shift D=b[6] clk=clk Q=b_st0[6]
+.subckt shift D=b_st0[6] clk=clk Q=b_st1[6]
+
+# Pipeline waddr
+.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0]
+.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0]
+.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1]
+.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1]
+.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2]
+.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2]
+.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3]
+.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3]
+.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4]
+.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4]
+.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5]
+.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5]
+# Pipeline wen
+.subckt shift D=wen clk=clk Q=wen_st0
+.subckt shift D=wen_st0 clk=clk Q=wen_st1
+# End pipeline
+
+# Start adder
+.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0]
+.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1]
+.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2]
+.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3]
+.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4]
+.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5]
+.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6]
+.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB[7]
+# End adder
+
+# Start DPRAM
+.subckt dpram clk=clk wen=wen_st1 ren=ren \
+waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \
+waddr[5]=waddr_st1[5] waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 waddr[9]=zero00 waddr[10]==zero00 \
+raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \
+raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 raddr[9]=zero00 raddr[10]=zero00 \
+d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \
+d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \
+d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \
+d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \
+d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \
+d_in[30]=zero00 d_in[31]=zero00 \
+d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \
+d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \
+d_out[6]=q[6] d_out[7]=q[7] d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \
+d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \
+d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \
+d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \
+d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn \
+d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn
+# End DPRAM
+
+# Start global variable
+.names zero00
+0
+# End global variable
+
+
+.end
+
+# Start blackbox definition
+.model dpram
+.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \
+ waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \
+ raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \
+ d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \
+ d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \
+ d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \
+ d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \
+ d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \
+ d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \
+ d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \
+ d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63]
+.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \
+ d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \
+ d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \
+ d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \
+ d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \
+ d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \
+ d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \
+ d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \
+ d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \
+ d_out[63]
+.blackbox
+.end
+
+
+.model adder
+.inputs a b cin
+.outputs cout sumout
+.blackbox
+.end
+
+
+.model shift
+.inputs D clk
+.outputs Q
+.blackbox
+.end
+# End blackbox definition
--- a/ERI_demo/pipelined_8b_adder.v
+++ b/ERI_demo/pipelined_8b_adder.v
@ -0,0 +1,63 @@
+/////////////////////////////////////
+//                                 //
+//    ERI summit demo-benchmark    //
+//      pipelined_8b_adder.v       //
+//          by Aurelien            // 
+//                                 //
+/////////////////////////////////////
+
+`timescale 1 ns/ 1 ps
+
+module pipelined_8b_adder(
+	clk,
+	raddr,
+	waddr,
+	ren,
+	wen,
+	a,
+	b,
+	q );
+
+	input clk;
+	input[5:0] raddr;
+	input[5:0] waddr;
+	input ren;
+	input wen;
+	input[6:0] a;
+	input[6:0] b;
+	output[7:0] q;
+
+	reg[63:0] ram[7:0];
+	reg[6:0] a_st0;
+	reg[6:0] a_st1;
+	reg[6:0] b_st0;
+	reg[6:0] b_st1;
+	reg[8:0] waddr_st0;
+	reg[8:0] waddr_st1;
+	reg wen_st0;
+	reg wen_st1;
+	reg[7:0] q_int;
+
+	wire[7:0] AplusB;
+
+	assign AplusB = a_st1 + b_st1;
+	assign q = q_int;
+
+	always@(posedge clk) begin
+		waddr_st0 <= waddr;
+		waddr_st1 <= waddr_st0;
+		a_st0 <= a;
+		a_st1 <= a_st0;
+		b_st0 <= b;
+		b_st1 <= b_st0;
+		wen_st0 <= wen;
+		wen_st1 <= wen_st0;
+		if(wen_st1) begin
+			ram[waddr_st1] <= AplusB;
+		end
+		if(ren) begin
+			q_int <= ram[raddr];
+		end
+	end
+
+endmodule
--- a/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v
+++ b/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v
@ -0,0 +1,219 @@
+`timescale 1 ns/ 100 ps
+
+`include "OPENFPGAPATHKEYWORD/ERI_demo/pipelined_8b_adder.v"
+
+module pipelined_8b_adder_top_formal_verification_random_tb();
+    reg clk;
+    reg[5:0] raddr;
+    reg[5:0] waddr;
+    reg ren;
+    reg wen;
+    reg[6:0] a;
+    reg[6:0] b;
+    wire[7:0] q_gfpga;
+    wire[7:0] q_bench;
+    reg[7:0] q_flag;
+
+    pipelined_8b_adder_top_formal_verification DUT(
+        .clk_fm     (clk),
+        .raddr_0__fm (raddr[0]),
+        .raddr_1__fm (raddr[1]),
+        .raddr_2__fm (raddr[2]),
+        .raddr_3__fm (raddr[3]),
+        .raddr_4__fm (raddr[4]),
+        .raddr_5__fm (raddr[5]),
+        .waddr_0__fm (waddr[0]),
+        .waddr_1__fm (waddr[1]),
+        .waddr_2__fm (waddr[2]),
+        .waddr_3__fm (waddr[3]),
+        .waddr_4__fm (waddr[4]),
+        .waddr_5__fm (waddr[5]),
+        .ren_fm     (ren),
+        .wen_fm     (wen),
+        .a_0__fm     (a[0]),
+        .a_1__fm     (a[1]),
+        .a_2__fm     (a[2]),
+        .a_3__fm     (a[3]),
+        .a_4__fm     (a[4]),
+        .a_5__fm     (a[5]),
+        .a_6__fm     (a[6]),
+        .b_0__fm     (b[0]),
+        .b_1__fm     (b[1]),
+        .b_2__fm     (b[2]),
+        .b_3__fm     (b[3]),
+        .b_4__fm     (b[4]),
+        .b_5__fm     (b[5]),
+        .b_6__fm     (b[6]),
+        .out_q_0__fm     (q_gfpga[0]),
+        .out_q_1__fm     (q_gfpga[1]),
+        .out_q_2__fm     (q_gfpga[2]),
+        .out_q_3__fm     (q_gfpga[3]),
+        .out_q_4__fm     (q_gfpga[4]),
+        .out_q_5__fm     (q_gfpga[5]),
+        .out_q_6__fm     (q_gfpga[6]),
+        .out_q_7__fm     (q_gfpga[7])
+    );
+
+    pipelined_8b_adder ref0(
+        .clk    (clk),
+        .raddr  (raddr),
+        .waddr  (waddr),
+        .ren    (ren),
+        .wen    (wen),
+        .a      (a),
+        .b      (b),
+        .q      (q_bench)
+    );
+
+	integer nb_error = 0;
+	integer count = 0;
+	integer lim_max = 64 - 1;
+	integer write_complete = 0;
+
+//----- Initialization
+  initial begin
+    clk <= 1'b0;
+    a <= 7'h00;
+    b <= 7'h00;
+    wen <= 1'b0;
+    ren <= 1'b0;
+    waddr <= 9'h000;
+    raddr <= 9'h000;
+    while(1) begin
+      #2.5
+      clk <= !clk;
+    end
+  end
+
+//----- Input Stimulis
+  always@(negedge clk) begin
+	if(write_complete == 0) begin
+	  wen <= 1'b1;
+	  ren <= 1'b0;
+	  count <= count + 1;
+	  waddr <= waddr + 1;
+	  if(count == lim_max) begin
+		write_complete = 1;
+	  end
+	end else begin
+	  wen <= $random;
+	  ren <= $random;
+	  waddr <= $random;
+	  raddr <= $random;
+	end
+	a <= $random;
+	b <= $random;
+  end
+
+
+  always@(negedge clk) begin
+    if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin
+      q_flag[0] <= 1'b1;
+    end else begin
+      q_flag[0] <= 1'b0;
+    end
+    if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin
+      q_flag[1] <= 1'b1;
+    end else begin
+      q_flag[1] <= 1'b0;
+    end
+    if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin
+      q_flag[2] <= 1'b1;
+    end else begin
+      q_flag[2] <= 1'b0;
+    end
+    if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin
+      q_flag[3] <= 1'b1;
+    end else begin
+      q_flag[3] <= 1'b0;
+    end
+    if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin
+      q_flag[4] <= 1'b1;
+    end else begin
+      q_flag[4] <= 1'b0;
+    end
+    if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin
+      q_flag[5] <= 1'b1;
+    end else begin
+      q_flag[5] <= 1'b0;
+    end
+    if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin
+      q_flag[6] <= 1'b1;
+    end else begin
+      q_flag[6] <= 1'b0;
+    end
+    if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin
+      q_flag[7] <= 1'b1;
+    end else begin
+      q_flag[7] <= 1'b0;
+    end
+  end
+
+
+  always@(posedge q_flag[0]) begin
+      if(q_flag[0]) begin
+        nb_error = nb_error + 1;
+        $display("Mismatch on q_gfpga[0] at time = %t", $realtime);
+      end
+  end
+  always@(posedge q_flag[1]) begin
+      if(q_flag[1]) begin
+        nb_error = nb_error + 1;
+        $display("Mismatch on q_gfpga[1] at time = %t", $realtime);
+      end
+  end
+  always@(posedge q_flag[2]) begin
+      if(q_flag[2]) begin
+        nb_error = nb_error + 1;
+        $display("Mismatch on q_gfpga[2] at time = %t", $realtime);
+      end
+  end
+  always@(posedge q_flag[3]) begin
+      if(q_flag[3]) begin
+        nb_error = nb_error + 1;
+        $display("Mismatch on q_gfpga[3] at time = %t", $realtime);
+      end
+  end
+  always@(posedge q_flag[4]) begin
+      if(q_flag[4]) begin
+        nb_error = nb_error + 1;
+        $display("Mismatch on q_gfpga[4] at time = %t", $realtime);
+      end
+  end
+  always@(posedge q_flag[5]) begin
+      if(q_flag[5]) begin
+        nb_error = nb_error + 1;
+        $display("Mismatch on q_gfpga[5] at time = %t", $realtime);
+      end
+  end
+  always@(posedge q_flag[6]) begin
+      if(q_flag[6]) begin
+        nb_error = nb_error + 1;
+        $display("Mismatch on q_gfpga[6] at time = %t", $realtime);
+      end
+  end
+  always@(posedge q_flag[7]) begin
+      if(q_flag[7]) begin
+        nb_error = nb_error + 1;
+        $display("Mismatch on q_gfpga[7] at time = %t", $realtime);
+      end
+  end
+
+  initial begin
+    $dumpfile("pipelined_8b_adder_formal.vcd");
+    $dumpvars(1, pipelined_8b_adder_top_formal_verification_random_tb);
+  end
+
+  initial begin
+    $timeformat(-9, 2, "ns", 20);
+    $display("Simulation start");
+    #1500 // Can be changed by the user for his need
+    if(nb_error == 0) begin
+      $display("Simulation Succeed");
+    end else begin
+      $display("Simulation Failed with %d error(s)", nb_error);
+    end
+    $finish;
+  end
+
+endmodule
--- a/README.md
+++ b/README.md
@ -1,23 +1,28 @@
-# Getting Started with FPGA-SPICE
+# Getting Started with OpenFPGA

 [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA)
 [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)

 ## Introduction

-FPGA-SPICE is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of heterogeneous architectures.
+OpenFPGA is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.

 ## Compilation

-The different ways of compiling can be found in the **./compilation** folder. 
+The different ways of compiling can be found in the **./compilation** folder.

-We currently implemented it for:
+**Compilation steps:**
+1. Create a folder named build in OpenPFGA repository (mkdir build && cd build)
+2. Create Makefile in this folder using cmake (cmake ..)
+3. Compile the tool and its dependencies (make)

-1. Ubuntu 18.04
-2. Red Hat 7.5
-3. MacOS High Sierra 10.13.4
+*We currently implemented OpenFPGA for:*

-Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.
+*1. Ubuntu 18.04*
+*2. Red Hat 7.5*
+*3. MacOS High Sierra 10.13.4*
+
+*Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.*

 ## Documentation
 OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options.
--- a/compilation/macos_compilation.md
+++ b/compilation/macos_compilation.md
@ -32,9 +32,9 @@ This will show the different options that can be used. Our modifications concern

 A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog

-`source ./go.sh`
+`source ./go_fpga_verilog.sh`

-This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
+This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
 For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).

 As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.
--- a/compilation/red_hat_compilation.md
+++ b/compilation/red_hat_compilation.md
@ -32,9 +32,9 @@ This will show the different options that can be used. Our modifications concern

 A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog

-`source ./go.sh`
+`source ./go_fpga_verilog.sh`

-This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
+This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
 For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).

 As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.
--- a/compilation/ubuntu_compilation.md
+++ b/compilation/ubuntu_compilation.md
@ -29,9 +29,9 @@ This will show the different options that can be used. Our modifications concern

 A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog

-`source ./go.sh`
+`source ./go_fpga_verilog.sh`

-This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
+This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
 For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).

 As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.
--- a/docs/source/eda_flow.rst
+++ b/docs/source/eda_flow.rst
@ -18,7 +18,6 @@ FPGA-Bitstream is the part of the flow in charge of the functional verification

 How to compile
 ==============
-Running the Makefile in the root of the released package can compile all the source codes. 
 Guides can be found in the *compilation* directory in the main folder. We tested it for MacOS High Sierra 10.13.4, Ubuntu 18.04 and Red Hat 7.5. This list is not exhaustive as other distributions could work as well.

 As a general rule, the compilation follows these steps:
@ -31,21 +30,24 @@ If you need the full flow:

 2) Go into the folder you just cloned and make the different submodules through a global Makefile:
 cd OpenFPGA 
-make
-OR 
-make -j 
-(if you have multiple cores, this will make the compilation way faster.) 
+mkdir build (*if folder doesn't already exist*)
+cd build
+cmake ..
+make OR make -j (*if you have multiple cores, this will make the compilation way faster*) 

 If you only need vpr:
-cd OpenFPGA/vpr7_x2p
-make/make -j
+cd OpenFPGA 
+mkdir build (if folder doesn't already exist)
+cd build
+cmake ..
+make vpr/make vpr -j

 3) Architectures, circuits and already written scripts exist to allow you to test the flow without having to provide any new information to the system. For this:
-cd vpr7_x2p (if not done already)
+cd vpr7_x2p
 cd vpr
-source ./go.sh
+source ./go_fpga_verilog/spice.sh

-go.sh is a script linking to a testing architecture and a simple circuit. The output will be in the folders spice_demo and verilog_demo.
+They are scripts linking to a testing architecture and a simple circuit.

 4) If you only need to see the new options implemented in vpr, do:
 ./vpr
--- a/docs/source/fpga_verilog/command_line_usage.rst
+++ b/docs/source/fpga_verilog/command_line_usage.rst
@ -8,11 +8,12 @@ FPGA-Verilog Supported Options::
 	--fpga_verilog
 	--fpga_verilog_dir <directory_path_of_dumped_verilog_files>
 	--fpga_verilog_include_timing
-	--fpga_verilog_init_sim
-	--fpga_verilog_print_modelsim_autodeck
-	--fpga_verilog_modelsim_ini_path <string>
+	--fpga_verilog_include_signal_init
+	--fpga_verilog_print_modelsim_autodeck <modelsim_ini_path>
 	--fpga_verilog_print_top_testbench 
-	--fpga_verilog_print_top_auto_testbench <path_to_the_verilog_benchmark>
+	--fpga_verilog_print_autocheck_top_testbench <reference_verilog_file_path>
+	--fpga_verilog_print_formal_verification_top_netlist
+	--fpga_verilog_include_icarus_simulator


 .. csv-table:: Commmand-line Options of FPGA-Verilog
@ -20,7 +21,8 @@ FPGA-Verilog Supported Options::
   :widths: 15, 30

   "--fpga_verilog", "Turn on the FPGA-Verilog."
-   "--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to. <dir_path> is the destination directory."
+<<<<<<< HEAD
+   "--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to <dir_path> is the destination directory."
   "--fpga_verilog_include_timing", "Includes the timings found in the XML file."
   "--fpga_verilog_init_sim", "Initializes the simulation for ModelSim."
   "--fpga_verilog_print_modelsim_autodeck", "Generates the scripts necessary to the ModelSim simulation."
@ -28,6 +30,17 @@ FPGA-Verilog Supported Options::
   "--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA. Determines the type of autodeck."
   "--fpga_verilog_print_top_auto_testbench \
   <path_to_the_verilog_benchmark>", "Prints the testbench associated with the given benchmark. Determines the type of autodeck."
+=======
+   "--fpga_verilog_dir <dir_path>", "Specify the directory where all the Verilog files will be outputted to. <dir_path> is the destination directory."
+   "--fpga_verilog_include_timing", "Includes the timings found in the XML architecture description file."
+   "--fpga_verilog_include_signal_init", "Set all nets to random value to be close of a real power-on case"
+   "--fpga_verilog_print_modelsim_autodeck <modelsim_ini_path>", "Generates the scripts necessary to the ModelSim simulation and specify the path to modelsim.ini file."
+   "--fpga_verilog_print_top_testbench", "Prints the full-chip-level testbench for the FPGA, which includes programming phase and operationg phase (random patterns)."
+   "--fpga_verilog_print_autocheck_top_testbench \
+   <reference_verilog_file_path>", "Prints a testbench stimulating the generated FPGA and the initial benchmark to compare stimuli responses, which includes programming phase and operationg phase (random patterns)"
+   "--fpga_verilog_print_formal_verification_top_netlist", "Prints a Verilog top file compliant with formal verification tools. With this top file the FPGA is initialy programmed. It also prints a testbench with random patterns, which can be manually or automatically check regarding previous options."
+   "--fpga_verilog_include_icarus_simulator", "Activates waveforms .vcd file generation and simulation timeout, which are required for Icarus Verilog simulator"
+>>>>>>> f56adc681567b73c7826228641e089482dffc009

 .. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are: 

--- a/docs/source/fpga_verilog/file_organization.rst
+++ b/docs/source/fpga_verilog/file_organization.rst
@ -1,15 +1,20 @@
 Hierarchy of Verilog Output Files
 ============================

-All the generated Verilog Netlists are located in the <verilog_dir> as you specify in the command-line options. Under the <verilog_dir>, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules. 
+All the generated Verilog Netlists are located in the <verilog_dir>/SRC as you specify in the command-line options. Under the <verilog_dir>/SRC, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules. 

 .. csv-table:: Folder hierarchy of FPGA-Verilog
-   :header: "Folder", "Content" 
+   :header: "File/Folder", "Content" 
   :widths: 10, 20
        
   "name_top.v", "Contains the top module and calls all the other .v files"   
   "name.bitstream", "Only if --fpga_verilog_print_top_testbench or --fpga_verilog_print_top_auto_testbench is chosen. Contains the bitstream programming the generated FPGA."
-   "name_top_tb.v", "Only if --fpga_verilog_print_top_testbench or --fpga_verilog_print_top_auto_testbench is chosen. Contains the testbench used for the simulation."
+   "name_top_tb.v", "Only if --fpga_verilog_print_top_testbench. Contains a testbench used for the simulation."
+   "name_autocheck_top_tb.v", "Only if --fpga_verilog_print_autocheck_top_testbench is chosen. Contains a testbench used for the simulation."
+   "name_formal_random_top_tb.v", "Only if --fpga_verilog_print_formal_verification_top_netlist is chosen. Contains a testbench used for the simulation."
+   "name_top_formal_verification.v", "Only if --fpga_verilog_print_formal_verification_top_netlist is chosen. Contains a top fil used for formal verification and by name_formal_random_top_tb.v."
+   "fpga_defines.v", "Contains all the defines set as 'include_timing'"
+   "name_include_netlists.v", "Contains all the netlists and defines paths used for the simulation."
   "lb", "Logic Block. Contains all the CLBs. The logic_block.v includes all the CLB and is called by the top module afterward."
   "routing", "Contains all the routing in the circuit. You can find in it the Switch Boxes, the Connection Blocks and the routing needed to connect the different blocks. The routing.v file packs them all and is called by the top module."
   "sub_modules", "Contains the modules generated by the flow to build the CLBs."
--- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
+++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
--- a/fpga_flow/scripts/fpga_flow.pl
+++ b/fpga_flow/scripts/fpga_flow.pl
@ -162,6 +162,7 @@ sub print_usage()
  print "      \t-vpr_fpga_x2p_rename_illegal_port : turn on renaming illegal ports option of VPR FPGA SPICE\n";
  print "      \t-vpr_fpga_x2p_signal_density_weight <float>: specify the option signal_density_weight of VPR FPGA SPICE\n";
  print "      \t-vpr_fpga_x2p_sim_window_size <float>: specify the option sim_window_size of VPR FPGA SPICE\n";
+  print "      \t-vpr_fpga_x2p_compact_routing_hierarchy : allow routing block modularization\n";
  print "      [ VPR - FPGA-SPICE Extension ] \n";
  print "      \t-vpr_fpga_spice <task_file> : turn on SPICE netlists print-out in VPR, specify a task file\n";
  print "      \t-vpr_fpga_spice_sim_mt_num <int>: specify the option sim_mt_num of VPR FPGA SPICE\n";
@ -344,6 +345,7 @@ sub opts_read()
  &read_opt_into_hash("vpr_fpga_x2p_rename_illegal_port","off","off");
  &read_opt_into_hash("vpr_fpga_x2p_signal_density_weight","on","off");
  &read_opt_into_hash("vpr_fpga_x2p_sim_window_size","on","off");
+  &read_opt_into_hash("vpr_fpga_x2p_compact_routing_hierarchy","off","off");
  &read_opt_into_hash("vpr_fpga_spice_sim_mt_num","on","off");
  &read_opt_into_hash("vpr_fpga_spice_print_component_tb","off","off");
  &read_opt_into_hash("vpr_fpga_spice_print_grid_tb","off","off");
@ -1333,6 +1335,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
    if ("on" eq $opt_ptr->{vpr_fpga_x2p_sim_window_size}) {
      $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_sim_window_size $opt_ptr->{vpr_fpga_x2p_sim_window_size_val}";
    }
+    if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) {
+      $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy";
+    }
    if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) {
      $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}";
    }