Update tutorial

fpga_flow/benchmarks/List/tuto_benchmark.txt

@@ -0,0 +1,2 @@
+# Circuit Names, fixed routing channel width, 
+s298/*.v, 200

fpga_flow/configs/tutorial/tuto.conf

@@ -0,0 +1,30 @@
+# Standard Configuration Example
+[dir_path]
+script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
+benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC
+yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
+odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
+cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
+abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
+abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
+abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
+mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
+m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
+mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
+vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
+rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial
+ace_path = OPENFPGAPATHKEYWORD/ace2/ace
+
+[flow_conf]
+flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
+vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
+mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
+m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
+mpack2_arch = K6_pattern7_I24.arch
+power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
+
+[csv_tags]
+mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
+mpack2_tags = BLE Number:|BLE Fill Rate: 
+vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
+vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff

fpga_flow/tuto_fpga_flow.sh

@@ -0,0 +1,31 @@
+#! /bin/bash
+# Exit if error occurs
+set -e
+# Make sure a clear start
+pwd_path="$PWD"
+task_name="tuto"
+config_file="$pwd_path/configs/tutorial/${task_name}.conf" 
+bench_txt="$pwd_path/benchmarks/List/tuto_benchmark.txt"
+rpt_file="$pwd_path/csv_rpts/fpga_spice/${task_name}.csv"
+
+verilog_path="${pwd_path}/${task_name}_Verilog"
+
+ff_keyword="FFPATHKEYWORD"
+ff_path="${pwd_path}/vpr7_x2p/vpr/Verilognetlists/ff.v"
+dir_keyword="GENERATED_DIR_KEYWORD"
+
+rm -rf ${pwd_path}/results_OpenPithon
+cd ${pwd_path}/scripts
+
+# Replace keyword in config and architecture files
+perl rewrite_path_in_file -i $config_file	# Replace OPENFPGAPATHKEYWORD in the config file
+perl rewrite_path_in_file -i $architecture_template -o $architecture_generated	# Replace OPENFPGAPATHKEYWORD in the architecture file
+perl rewrite_path_in_file -i $architecture_generated -k $ff_keyword $ff_path	# Set the ff path in the architecture file
+perl rewrite_path_in_file -i $ff_path -k $dir_keyword $verilog_path	# Set the define path in the ff.v file
+
+
+# SRAM FPGA
+# TT case 
+perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -end_flow_with_test
+
+echo "Netlists successfully generated and tested"

tutorials/tutorial.md

@@ -16,7 +16,7 @@ OpenFPGA repository is organized as follow:
 * **yosys**: opensource synthesys tool
 * **fpga_flow**: scripts and dependencies to run the complete flow
 
-## 1. FPGA flow
+##   1. FPGA flow
 
 The folder is organized as follow:
 * **arch**: contains architectures description files
@@ -35,13 +35,13 @@ fpga_flow.pl has dependencies which need to be configured. They are:
 * configuration file, which provides dependencies path and flow type
 * benchmark list file
 
-### Configuration file
+### a. Configuration file
 
 In this file paths have to be full path. Relative path could lead to errors.<br />
 The file is organized in 3 parts: 
-* dir_path: provides all the tools and repository path
-* flow_conf: provides information on how the flow run
-* csv_tags: *to complete*
+* **dir_path**: provides all the tools and repository path
+* **flow_conf**: provides information on how the flow run
+* **csv_tags**: *to complete*
 
 While empty the file is as follow:
 
@@ -77,15 +77,32 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St
 
 *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf*
 
-### Benchmark list
+###   b. Benchmark list
 
 The benchmark folder contains 3 sub-folders:
-* Blif: contains .blif and .act of benchmarks
-* List: contains all benchmark list files
-* Verilog: contains Verilog designs
+* **Blif**: contains .blif and .act of benchmarks
+* **List**: contains all benchmark list files
+* **Verilog**: contains Verilog designs
 
 Blif and Verilog folders are organized by folders with name of projects. **Folder, top module and top module file must share the same name.**<br />
 The benchmark list file can contain as many benchmark as available in a same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:<br />
 top_module/*.v,<int_value>; where <int_value> is the number ofchannel/wire between each blocks.
 
 *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
+
+###   c. Running fpga_flow.pl
+
+Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".<br />
+Few options are only in fpga_flow:
+* -N: number of LUT per CLB
+* -K: LUT size/ number of input
+* -rpt <path>: wherever fpga_flow will write its report
+* -ace_d <int_value>: specifies inputs average probability of switching
+* -multi_thread <int_value>: specifies number of core to use
+* -end_flow_with_test: uses Icarus Verilog to verify generated netlist
+
+*An example of script can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh*
+
+
+
+