Commit Graph

4844 Commits

Author SHA1 Message Date
Tim Newsome 1f512eac32 Merge commit 'd4575b647a3603200a9bb4a784d170f792ab88d0' into from_upstream
Change-Id: Iaa299c50b338089f1b3b7ff7d89fad39ac20a7c1
2023-12-05 14:36:04 -08:00
Tim Newsome a63b270b38 Merge commit 'a9080087d82688043ca216d50926228d09631297' into from_upstream
Change-Id: I83a33c1022f8d1a7670ded62f16ec999fc4ef525
2023-12-05 14:35:54 -08:00
Tim Newsome 64f5ec0408 Merge commit 'eba5d211937d1ebcb3669810ff63ad1083600b67' into from_upstream
Conflicts:
	src/target/breakpoints.c

Change-Id: I62b67651956ba3e1dba791ad129e0853517cd7ba
2023-12-05 14:35:35 -08:00
Tim Newsome db645af8da Merge commit 'bcaac692d0fce45189279a4c80cbd6852e4bbf4e' into from_upstream
Conflicts:
	src/target/breakpoints.c

Change-Id: I815ac06fbe74398fad307112e95fde5c49bbc590
2023-12-05 13:47:42 -08:00
Marc Schink 119a533862 target/target: Fix 'wp' command usage
While at it, fix the 'wp' command documentation.

Change-Id: I70f3110e8ce286051f8f810260f1857b2285e634
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8022
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-12-01 22:23:49 +00:00
Evgeniy Naydanov 73d62f3f0c target: clarify usage of `coreid`
By definition in `target/target.h`, `coreid` is not a unique identifier
of a target -- it can be the same for targets on different TAPs.

Change-Id: Ifce78da55fffe28dd8b6b06ecae7d8c4e305c0a2
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7997
Tested-by: jenkins
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-12-01 22:23:13 +00:00
Walter Ji 15038ab51a target/mips32: pracc write cp0 status register first
When user requested a change on cp0 status register,
it may contain changes on EXL/ERL bits, and changes on
these bits could lead to differnt behaviours on writing
to other cp0 registers.

Change-Id: Ic83039988c29c06ee134226b52de943c46d19da2
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7914
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-12-01 22:21:40 +00:00
Evgeniy Naydanov 560c338526 target/riscv: avoid using VLA in `log_debug_reg()`
OpenOCD style guide(`doc/manual/style.txt`) prohibits use of VLA:

> - use malloc() to create dynamic arrays. Do @b not use @c alloca
> or variable length arrays on the stack. non-MMU hosts(uClinux) and
> pthreads require modest and predictable stack usage.

Change-Id: I12e4a5087fd056d69866137237af6deca27f5d33
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-12-01 16:45:48 +03:00
Evgeniy Naydanov f5b8862a76 target/riscv: report helpfull location during register decode
`LOG_TARGET_DEBUG()` reports file, line and function name at the call
site. This information is not helpfull if it always points to the same
location inside `log_debug_reg()`.

Change-Id: Ib73be0344fb5c80c9ac8e5fdee1084d405522eb7
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-12-01 16:45:30 +03:00
Parshintsev Anatoly 10af616067 fix erroneously-resolved merge conflict
Change-Id: I4278e3e444eec93c418dfe153f60404f9848a20a
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-11-29 20:51:42 +03:00
Kirill Radkin c5185e9219 breakpoints: Fix endless loop in bp/wp_clear_target
If we can't remove bp/wp, we will stuck in endless loop

Change-Id: I44c0a164db1d15c0a0637d33c75087a49cf5c0f4
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7940
Tested-by: jenkins
Reviewed-by: Anatoly P <kupokupokupopo@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-27 10:09:35 -08:00
Tim Newsome 84bcf9aa8b Merge commit '4b1ea8511a7da9d7201df40302e3341c6e97ffdd' into from_upstream
Change-Id: I59366e08a4ac7e443e426b5fd6727c649f1ac9d5
2023-11-27 10:04:09 -08:00
Tim Newsome 0deaa63f50 Merge commit '022e438292de992cc558f268b2679e76ad313db6' into from_upstream
There was a big conflict with this one incoming change. This version of
the code passes all the tests (which don't test for the changed behavior
at all AFAIK), and at least passes errors back everywhere.

Conflicts:
	src/target/breakpoints.c

Change-Id: I72f75a3e08deda7e624e8bb82e1a9ea07a7a9276
2023-11-27 10:03:56 -08:00
Marc Schink 1b0b07baab target: Throw error in 'debug_reason' command
Instead of returning an 'error string', throw an error. This makes it
much easier to handle errors in Tcl scripts or in tools that use Tcl RPC.

Change-Id: I75c48750cfad7430fa5e6bc88fe04ebd59d34cea
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8006
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-24 21:40:49 +00:00
Evgeniy Naydanov be5cfdc86b target: remove `target_number`
Change-Id: Id36e5ad2967303483392fd2670630289ecde2553
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7998
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2023-11-24 21:07:14 +00:00
Tim Newsome 92213132a6 Merge commit '18281b0c497694d91c5608be54583172838be75c' into from_upstream
Change-Id: I05cd5ef9b04fa61a27321ae9b6a4fecabe3dee80
2023-11-20 12:30:19 -08:00
Tobias Diedrich 62b526dbbd mips32: MIPS32_OP_SRL was using SRA opcode.
The mips opcode macro for the SRL opcode was using the wrong constant
value:

SRA -- Shift right arithmetic
Encoding: 0000 00-- ---t tttt dddd dhhh hh00 0011

SRL -- Shift right logical
Encoding: 0000 00-- ---t tttt dddd dhhh hh00 0010

This corrects the opcode constant for SRL and adds the SRA opcode for
completeness.

There is only one user of MIPS32_OP_SRL in src/flash/nor/cfi.c:
Since the mask constant (0x00000080 for the DQ7 mask) shifted in this
case would never have the sign bit set, it worked fine even though it
was accidentally using the SRA opcode instead of SRL.

Change-Id: I0a80746e2075c7df1ce35b9db00d9d0b997a3feb
Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/3613
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2023-11-18 11:29:49 +00:00
Peter Collingbourne 393da819b1 aarch64: Use 64-bit reads/writes to access SCTLR_EL1
We were previously inadvertently clearing the top 32 bits of SCTLR_EL1
during read_memory/write_memory as a result of using 32-bit operations
to access the register and because the fields used to temporarily
store the register were 32-bit. Fix it.

Change-Id: I657d7f949e1f7ab6bf90609e3f91cae09cade31a
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7939
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-18 11:21:38 +00:00
Peter Collingbourne ee96a95d44 openocd: src/target: Correctly handle CCSIDR_EL1.Associativity=0
Associativity=0 means that only one CMO is needed for all ways.
It could also mean that the cache is 1-way, but this is less likely.

Currently Associativity=0 causes us to hang in the while loop in
decode_cache_reg. Fix it by skipping the loop in this case. We can let
way_shift be set to the arbitrary value of 0 because in the case where
Associativity=0 we only ever shift 0 by it before ORing it into the
CMO operand.

Change-Id: I7c1de68d33f6b3ed627cbb1e2401d43185e4c1e3
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7916
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-18 11:20:56 +00:00
Marek Vrbka 851d1ad87a breakpoints: Add target logging to breakpoints and watchpoints
This patch adds target logging to breakpoint
handling code. This makes it easier to
debug multicore/multithread systems.

Change-Id: I6bea8079a457070a8f63d0ce381a4ece6f5a190a
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7922
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-11-18 11:20:11 +00:00
Kirill Radkin 7c60f6593e breakpoints: Fix endless loop in bp/wp_clear_target
If we can't remove bp/wp, we will stuck in endless loop

Change-Id: I44c0a164db1d15c0a0637d33c75087a49cf5c0f4
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7940
Tested-by: jenkins
Reviewed-by: Anatoly P <kupokupokupopo@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-18 11:19:45 +00:00
ianst f8096ce687 xtensa: update XDM register map for TRAX support
- Include additional debug module registers
- Add translation function for DM reg addr -> ID
- Add DM read/write commands

Signed-off-by: ianst <ianst@cadence.com>
Change-Id: If95419d24a9f27a40fa695c8c15326cdfd127ef1
Reviewed-on: https://review.openocd.org/c/openocd/+/7973
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-11-18 11:18:29 +00:00
Marc Schink 3862e07688 target: Remove break/watchpoints in target_destroy()
Break- and watchpoints are not removed when a target is destroyed
which introduces a memory leak.

Change-Id: I6143d48f7efd765b7752a12fdc337da3496d896f
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7956
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-18 11:16:53 +00:00
Antonio Borneo d4575b647a target: fix segmentation fault on target create
In the unusual (and even incorrect) case of running the command
target create ...
before defining an adapter and the associated transport, the
command causes a segmentation fault. E.g.:
	openocd -c 'target create cpu cortex-m -endian little'

Check that get_current_transport() returns a valid pointer before
referencing it.

Change-Id: I9796a7e92196ef3df5c7152b27c34102045dc9e7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7962
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2023-11-18 11:16:27 +00:00
Antonio Borneo b39072f2ef target: use boolean values for 'valid' and 'dirty' flags
Convert to boolean the remaining numeric assignment and comparison

Change-Id: Idc25221d93e85236185aab9ee36f0a379939c89c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7961
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
2023-11-18 11:16:06 +00:00
Tim Newsome af786c0eca
Merge pull request #963 from kr-sc/kr-sc/no-free-triggers
When an attempt to set watchpoint fails because there is no free triggers OpenOCD reports "unknown error"
2023-11-17 09:18:44 -08:00
Tim Newsome 334f690f2a
Merge pull request #958 from riscv/set_field_get_field
target/riscv: Replace [sg]et_field macros with functions.
2023-11-16 15:22:57 -08:00
Tim Newsome d5ea55cfca
Merge pull request #957 from riscv/sbbusyerror
target/riscv: Handle sbbusyerror in read_memory_bus_v1
2023-11-16 09:39:41 -08:00
Kirill Radkin fee2e04d90 When an attempt to set watchpoint fails because there is no free triggers OpenOCD reports "unknown error"
Now it returns `resource not available`

Change-Id: Ifbbd468bdf62023850690eb96fe8a16f4114e915
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-11-16 17:18:22 +03:00
Tim Newsome 08182bfc6b target/riscv: Handle sbbusyerror in read_memory_bus_v1
The existing code didn't seem to work right at all. I have spike
modifications that exercise these new cases. I'll merge those once this
has merged.

Change-Id: I89bd336f34f1b208a76f25b6b41fe3877800765b
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-11-15 11:27:32 -08:00
Tim Newsome 86b430b6b4 target/riscv: Replace [sg]et_field macros with functions.
Compilers are good at optimizing, and with functions it's abundantly
clear what all the types involved are. This change means we don't have
to be super careful about the type of values because of what the macro
might do to them that might cause overflow.

The only place where the return type matters is in printf-style
functions, and I made get_value32() for those cases where a change was
needed.

This should set the stage for simply copying the latest debug_defines.h
from the debug spec build again.

Change-Id: I5fb19d0cfc1e20137832a7b344b05db215ce00e1
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-11-15 11:12:09 -08:00
Evgeniy Naydanov 00320fd198 target/riscv: replace `__PRETTY_FUNCTION__` with `__func__`
The reasoning for the change:
* `__func__` is part of C99, `__PRETTY_FUNCTION__` is GNU extension.
* `__PRETTY_FUNCTION__` is defined to be the same as `__func__` for C
  sources by GCC documentation but differ for C++ sources (full
  signature instead of just a name).
* Currently Clang does support `__PRETTY_FUNCTION__`, though it uses
  GCC's C++ variant across C and C++.

Therefore using `__PRETTY_FUNCTION__` creates confusion and does not
provide any valueble information in the logs.

Change-Id: Ie0db6d73f602784b6752a30911dcef3dd7ee4594
2023-11-15 14:06:29 +03:00
Evgeniy Naydanov 3b0c654c67 target/riscv: dump_field() shouldn't always decode
Sometimes, the value from of some DMI scans has no meaning (e.g. when
`op` is read). Such values should not be decoded. To make the dumps more
consistent, `<no decoding available>` is printed when there is no
decoding for a register.

Change-Id: I415f06a5a80f2fc8fb8ab3f79132bdf0602c8ad6
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-11-15 14:06:29 +03:00
Tim Newsome 6de536bbb8
Merge pull request #961 from en-sc/en-sc/coreid-target-riscv
target/riscv: clarify usage of `coreid`
2023-11-13 09:45:58 -08:00
Peter Collingbourne 42441fd96c target: Add a debug_reason command
This allows programmatically determining the debug reason.

Change-Id: I0c3e85cebb6dc28fc0fc212beca84a484ac654a5
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7952
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-11-11 18:43:43 +00:00
Erhan Kurubas a9080087d8 target/breakpoints: make breakpoint_watchpoint_remove_all static
Fixes below Sparse tool warning.
warning: symbol 'breakpoint_watchpoint_remove_all' was not declared.
Should it be static?

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I4af1d5aa54abcb45f746b877513ba0b5fccbeb47
Reviewed-on: https://review.openocd.org/c/openocd/+/7955
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-11-11 18:05:46 +00:00
Evgeniy Naydanov 0f261188f1 target: fix a memory leak in image_open
Change-Id: I629be26e7752858091ad58c2b3b07f43e22e8c23
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7935
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-11-11 18:05:11 +00:00
Walter Ji d209598ce9 target/mips32: update mips32 config register parsing
Enhance `mips32_read_config_regs` to better detect MIPS32 ISA,
DSP, and FPU features, allowing user to get more detailed
target information.
Most of these information will be used in MIPS m/iAptiv support.

Change-Id: I23571a626ec64fa019acac91bdbfcb434373bfc1
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7911
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2023-11-11 18:04:19 +00:00
Marek Vrbka 7d1f132cea target: Fix get_reg, prevent returning invalid data
This patch forces a read of register from the target
in the get_reg command in case the register cache
does not hold a valid value at that moment.

Note that the command "reg" already handles it
correctly, no fix is needed there.

Change-Id: I75fad25188e94ee4e06162ab6d600ea24dbf590a
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7958
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-11-11 18:03:47 +00:00
Marc Schink f58b5ddaf2 target/target: Use boolean values for 'valid' flag
Change-Id: Ieaa25b9ef0997c0f75ddfb652325c1a9e53a8d8d
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7959
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-11-11 18:02:52 +00:00
Tim Newsome 1ea0e9b426
Merge pull request #928 from AnastasiyaChernikova/triggers
target/riscv: cache requests to trigger configuration
2023-11-10 12:12:03 -08:00
Evgeniy Naydanov 5ec9938c61 target/riscv: clarify usage of `coreid`
By definition in `target/target.h`, `coreid` is not a unique identifier
of a target -- it can be the same for targets on different TAPs.

Change-Id: Ifce78da55fffe28dd8b6b06ecae7d8c4e305c0a2
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-11-10 13:11:12 +03:00
Marek Vrbka 2357237815 target/riscv: Replace watchpoint value mask comparison value with macro.
This patch replaces ~(typeof(watchpoint->mask))0 with
WATCHPOINT_IGNORE_DATA_VALUE_MASK. This improves
readability and moves the RISCV target in line with
other targets.

Change-Id: I15ac4d4ee76098b304d9b22f720911ba4329c190
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-11-09 10:11:22 +01:00
Tim Newsome f119c1d480
Merge pull request #954 from riscv/from_upstream
Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' from upstream
2023-11-07 09:17:37 -08:00
Tim Newsome 5653f512a2
Merge pull request #952 from MarekVCodasip/stop-caching-dpc
target/riscv: Stop caching writes to DPC
2023-11-07 09:04:58 -08:00
Anastasiya Chernikova fea20e2bf5 target/riscv: cache requests to trigger configuration
Depending on configuration, the existing implementation of watchpoints is
rather inefficient for certain scenarios. Consider HW that:

1. triggers 0-3 can be used as instruction breakpoints
2. triggers 4-7 can be used as data breakpoints (watchpoints)
3.  NAPOT triggers are not supported.

Now, consider that we have a pending watchpoint. And we perform a "step"
operation. According to the current implementation:

* OpenOCD will disable watchpoints
* Perform a single-step
* Will try to restore the original watchpoints. It will need 12 attempts
to find a suitable trigger: (8 attempts to try NAPOT, and another 4 to try
GE+LE).

This patch introduces a dedicated cache for requests to triggers. It
significantly speeds things up, since we cache failed attempts and no
additional interactions with HW is necessary.

Change-Id: Ic272895eaa763a7ae84d14f7633790afd015ca9d
Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2023-11-07 14:51:49 +03:00
Tim Newsome b5bd88441c Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' into from_upstream
Conflicts:
	src/jtag/drivers/xds110.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg

Change-Id: If0c02817df03b7fd700cc84b4da2c02d36737d28
2023-11-06 09:25:46 -08:00
Tim Newsome c2f544c4f6 target/riscv: gdb_regno_name takes an enum.
Otherwise it won't compile for me. Not sure why that doesn't affect the
automated builds.

Change-Id: Ic66c743e1698c4c0772e5601723cb5c711b4fa5c
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-11-03 10:48:05 -07:00
Tim Newsome b75bfab026
Merge pull request #896 from AnastasiyaChernikova/ac-sc2
target/riscv: Adding register tables to make register names consiste
2023-11-03 10:30:35 -07:00
Tim Newsome 2676f05f2f
Merge pull request #947 from riscv/from_upstream
From upstream
2023-11-03 10:13:05 -07:00
Marek Vrbka adb9c3209e target/riscv: Stop caching writes to DPC
Since DPC is WARL (same rules as MEPC according to
the specification), it is possible that
writes to it won't result in the exact value present.
Therefore, writes to it shouldn't be cached, same as
with other WARL registers.

Change-Id: I818c0cef9727b999b7d84b19f9f42cd706c99d69
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-11-03 12:11:01 +01:00
Tim Newsome 20bcd83bca
Merge pull request #945 from kr-sc/kr-sc/fix-mmu-access-upstream
target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
2023-11-02 09:33:55 -07:00
Anastasiya Chernikova 805d394ff8 target/riscv: Adding register tables to make register names consistent
Added the ability to enter dimensionless registers

Change-Id: I1b781959ce4690ec65304142bd9a7c6f540b3e86
Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2023-11-02 17:21:59 +03:00
Tim Newsome e474d1d54a target/riscv: Prevent dump_field() reading uninitialized memory
Change-Id: I9ef8f2c2e9a824aa6595e8f20682c968ae5aed72
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-30 09:21:19 -07:00
Kirill Radkin 57c3f0d91c target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
Now:
1) If mmu is disabled, virt2phys succeeded and returns physical address
2) If mmu is enbaled, but translation fails, read/write_memory fails

Change-Id: I312309c660239014b3278cb77cadc5618de8e4de
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-30 15:59:41 +03:00
Tim Newsome f02fe0960c Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstream
Conflicts:
	HACKING
	src/target/riscv/riscv-013.c

Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
2023-10-27 09:00:59 -07:00
Tim Newsome 89260a5f1f
Merge pull request #942 from riscv/from_upstream
From upstream
2023-10-27 08:46:43 -07:00
Evgeniy Naydanov 57b67eda38 target/riscv: update debug register printers
Change-Id: I069bbe069a3aaa7fd3a4f6eccde40f813db33cc9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-10-25 19:16:36 +03:00
Walter Ji e887cfb9e8 target/mips32: check read regs result in save context
Add result check for mips32_pracc_read_regs in mips32_save_context.

Change-Id: Ie796d2b05a9feb11e246c2d0771b52cad4fb70db
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7932
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-25 01:34:00 +00:00
Walter Ji 18c64af135 target/mips32: rework mips core register related functions
Update mips core definitions.
Reworked mips core register structure and read/write function.
Add coprocessor0 register definitions for target configuration.

Change-Id: I59c1f4cc4020db8a78e8d79f7421b87382fa1709
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7864
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-25 01:33:10 +00:00
Tim Newsome 2d98ef5d13
Merge pull request #941 from kr-sc/kr-sc/fix-hgatp-mode-upstream
hgatp_mode in riscv_virt2phys_v defined by vsatp value
2023-10-24 07:57:37 -07:00
Tim Newsome af08d582b5 Merge commit 'e17fe4db0f256ee4fb97dcfd6b9f7f55c966b190' into from_upstream
Conflicts:
	src/flash/nor/drivers.c
	src/target/riscv/riscv.c

Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd
2023-10-23 12:29:21 -07:00
Tim Newsome 132e3faf1d
Merge pull request #940 from riscv/revert-908-disable-soft-bp-size-2-non-compressed
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported"
2023-10-23 11:45:50 -07:00
Kirill Radkin 109772012a hgatp_mode in riscv_virt2phys_v defined by vsatp value
Replace `vsatp` with `hgatp` (how it should be)

Change-Id: Ie548467b06d1fb266ccc56cbec1aff8d9f435973
2023-10-23 18:56:40 +03:00
Tim Newsome 3b0561d081
Merge pull request #935 from riscv/from_upstream
Merge down up to 0384fe5 from upstream.
2023-10-23 08:38:48 -07:00
Tim Newsome 912de786a4
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported" 2023-10-20 15:37:28 -07:00
Tim Newsome a495dd854c
Merge pull request #934 from kr-sc/kr-sc/revert-commit
Revert "target: Update messages connected with `examine`"
2023-10-17 09:46:31 -07:00
Kirill Radkin 6c96b9d8c3 Revert "target: Update messages connected with `examine`"
This reverts commit a3db93b1ce.

Reason for revert: https://github.com/riscv/riscv-openocd/pull/931#issuecomment-1761550506
2023-10-17 12:57:39 +03:00
Tim Newsome 53fcf14d83 Merge commit '0384fe5d596f42388f8b84d42959d899f29388ab' into from_upstream
Conflicts:
      .github/workflows/snapshot.yml
      src/rtos/FreeRTOS.c

Change-Id: I4c9ff887b69140e0f61cb3f75a2f2c1a12071320
2023-10-16 12:30:06 -07:00
Tim Newsome e1fa78d1b3
Merge pull request #929 from aap-sc/riscv
do not assume DTM version unless dtmcontrol is read successfully
2023-10-16 12:10:25 -07:00
Parshintsev Anatoly c7d1f0ddab target: check if target is not examined on reg command
Change-Id: I46093c85374986a36d10eaac38b98bd5e05835ca
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7841
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-10-14 12:06:40 +00:00
Marek Vrbka 7822260ed4 target: Change the watchpoint type print from number to letter
Previously, when listing the watchpoints, OpenOCD printed
numbers 0, 1 and 2 representing READ, WRITE and ACCESS type
watchpoints.

This patch changes it to 'r', 'w' and 'a'. This increases the
clarity as what type the watchpoint actually is.

Change-Id: I9eac72dfd0bb2a9596a5b0c080a3f584556ed599
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7909
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-14 12:02:57 +00:00
Marek Vrbka eba5d21193 breakpoints: add rwp all command
This patch adds the "all" option to the rwp command.
It removes all watchpoints, much like rbp all removes
all breakpoints.

Change-Id: Id58dd103085e558f17afa4a287888cf085566ca9
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7907
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-14 12:01:38 +00:00
Kirill Radkin bcaac692d0 target: Fix an issue with rwp/rbp command in smp targets
If wp/bp is missing at address rwp/rbp won't return zero code (on smp).
Now it fixed.

Fixes: 022e438292 ("target: Change policy of removing watchpoints/breakpoints.")

Change-Id: I3a3c245f7088fc23227b286d2191fc7f3edba702
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7910
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-14 11:59:34 +00:00
Florian Fainelli d27a3a00b8 arm_opcode: Add support for ARM MCRR/MRRC
Add support for the ARM MCRR/MRRC instructions which require the use of
two registers to transfer a 64-bit co-processor registers. We are going
to use this in a subsequent patch in order to properly dump 64-bit page
table descriptors that exist on ARMv7A with VMSA extensions.

We make use of r0 and r1 to transfer 64-bit quantities to/from DCC.

Change-Id: Ic4975026c1ae4f2853795575ac7701d541248736
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Michael Chalfant <michael.chalfant@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5228
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-14 11:55:42 +00:00
Tim Newsome beb705912b
Merge pull request #917 from kr-sc/kr-sc/disable-triggers-option
provide riscv-specific controls to disable triggers from being used for watchpoints
2023-10-11 12:34:07 -07:00
Tim Newsome 41d1ee3715
Merge pull request #931 from kr-sc/kr-sc/update-examine-messages
target: Update messages connected with `examine`
2023-10-11 12:33:38 -07:00
Parshintsev Anatoly 2f17449dff target: return error if attempting to access non-existing registers
Change-Id: Ic22edcab46d21dbc71f78275a78bdea9c2bcc394
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7886
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-10-07 14:43:59 +00:00
Artemiy Volkov d20304b3fb target/arc: do not invalidate icache when (un)setting breakpoints
Currently, instruction cache is being invalidated in
arc_{un,}set_breakpoint() regardless of whether the breakpoint's type is
HW or SW. For SW breakpoints, this has no net effect as the caches are
flushed as a by-product of overwriting instructions in main memory and
is thus merely unnecessary; but for HW breakpoints this invalidation is
not preceded by a flush and might lead to loss of data. This patch
removes the invalidate() call altogether to correct this undesired
behavior for HW breakpoints.

With this patch applied, all supported HW breakpoint tests from the gdb
testsuite are now passing with the arc-openocd backend.

Change-Id: I3d252b97f01f1a1e2bf0eb8fb257bdab0c544bc2
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7767
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-07 14:42:13 +00:00
Antonio Borneo bdf73617e7 armv8_dpm: fix registers read at debug entry
The comment above armv8_dpm_read_current_registers() doesn't match
the implementation, as the function reads all the registers from
ARMV8_PC and above.
The registers currently read are not relevant to answer to the
usual GDB initial request through the 'g' packet. Plus the lack of
differentiation per core state (AArch32 vs AArch64) causes the
read of not existing registers in AArch32 triggering errors, as
tentatively fixed by https://review.openocd.org/5517/

Fix the code to read the registers initially required by GDB.
Modify the comment to report the register list in AArch32 and in
AArch64.
Keep the extra checks inside the read loop, even if they are
mostly irrelevant; this could prevent errors if someone needs to
extend the number of registers to read.

The current implementation of the register's description in
OpenOCD does not allow to discriminate among AArch32 and AArch64
registers. Add a TODO comment to highlight it.

Change-Id: Icd47d93c19a9e1694a7b51bbc5ca7e21a578df41
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7887
Tested-by: jenkins
2023-10-07 14:39:12 +00:00
liangzhen 3f1339f8e8 target/riscv: use cacheable read/write function to handle DCSR
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-07 09:26:31 +08:00
Parshintsev Anatoly 2c4118ecea do not assume DTM version unless dtmcontrol is read successfully
Change-Id: I5f2003b7ac5ce87af6ca9a4fcb46140682a8cfdf
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-10-06 18:51:53 +03:00
Tim Newsome 599e0a22e8
Merge pull request #915 from riscv/dpc_print
target/riscv: Remove duplicate read PC message
2023-10-05 12:05:16 -07:00
Kirill Radkin a3db93b1ce target: Update messages connected with `examine`
Move `examine_attempted` flag to target struct to make it target specific.
`Info` messages for retry and `Error` messages for failure added.

Change-Id: Id2fbe7dc68d746c936c8412289d0d149fbd80d71
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-03 16:28:28 +03:00
Ahmed Boughanmi f76c8de910 target/cortex_m: support Infineon Cortex-M33 from SLx2 MCU
The secure microcontroller Infineon SLx2 uses a custom Cortex-M33.
The register CPUID reports value 0x490FDB00.

Reference link to the product:
Link: https://www.infineon.com/cms/en/about-infineon/press/market-news/2022/INFCSS202211-034.html

Change-Id: I8911712c55bd50e24ed53cf49958352f470027a5
Signed-off-by: Ahmed Boughanmi <boughanmi.external@infineon.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7879
Reviewed-by: Karl Palsson <karlp@tweak.au>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-10-02 14:50:50 +00:00
Marek Vrbka c6ab3abeee image: log error when unknown image type is specified
This patch adds error reporting when unknown image type is specified.
Previously, OpenOCD replied with an empty string.

Change-Id: I16220b1f5deb3b966a21731f0adf7911a78e8959
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7883
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-10-02 14:49:57 +00:00
Kirill Radkin e76a9b799d provide riscv-specific controls to disable triggers from beeing used for watchpoints
Add a new riscv specific commands to disable triggers

Change-Id: Ic1842085aa66851c740e0abcbfbe0adbe930920e
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-02 11:54:07 +03:00
Tim Newsome 2f1714789b
Merge pull request #921 from lz-bro/repeat_read-fix
target/riscv: support riscv repeat_read by sysbus access
2023-09-29 09:31:59 -07:00
Tim Newsome 75b5de67df
Merge pull request #918 from kr-sc/kr-sc/allow-to-query-status-dcsr-ebreak
openocd does not allow to query status of dcsr.ebreak{u,s,m}
2023-09-29 09:30:46 -07:00
Tim Newsome ef3be96ba1
Merge pull request #892 from en-sc/en-sc/register-printing
target/riscv: define register printers
2023-09-28 08:36:36 -07:00
Kirill Radkin ee2bc807eb openocd does not allow to query status of dcsr.ebreak{u,s,m}
Extend riscv set_ebreak* commands.
Now it can be called without args to print current value.

riscv_ebreak* flags are moved to riscv_info struct.

Change-Id: Ib46e6b6dfc0117599c7f6715c7aaf113e63bd7dc
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-09-26 11:52:30 +03:00
Tim Newsome 3acc277e49 target/riscv: Remove duplicate `read PC` message
Change-Id: Ie085758e3cf193f2671ea53fb82fd401d0c52d86
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-25 11:41:04 -07:00
Tim Newsome b5e57e1894
Merge pull request #913 from riscv/from_upstream
From upstream
2023-09-25 09:21:09 -07:00
Tomas Vanek 5fd4f2954d target/adi_v5_xxx: use ADIV5_DP_SELECT_APBANK
and DP_SELECT_DPBANK.
Use the defined symbols instead of magic numbers.

Change-Id: I19c86b183e57e42b96f76eed180c0492cd67bee1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7539
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-23 14:37:22 +00:00
Tomas Vanek f49bf1adb4 target/arm_adi_v5,jtag/drivers: rename ADIv5 only defines
DP_SELECT_APSEL and DP_SELECT_APBANK is no more used in ADIv6.

Change-Id: I4176574d46c6dc8eb3fe3aef6daab6e33492c050
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7538
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-23 14:36:57 +00:00
Evgeniy Naydanov 43ebdd47a5 target/riscv: define register printers
`riscv_debug_reg_to_s()` can be used to decode register value.  If the
pointer to buffer is `NULL` it does not print anything, just returns the
length of the string.

The format is:
`<register_value> { <field_name>=<field_value_name or field_value>, ..., }`

e.g:

`0x400382 { version=2, ... ndmresetpending=false, }`

`0x321009 { regno=0x1009, ... cmdtype=0, }`

Change-Id: I63733d8d36385d89ca15de1a43139134bc488c4f
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-22 16:26:28 +03:00
liangzhen a8ffda6e70 target/riscv: support riscv repeat_read by sysbus access
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-09-21 15:33:17 +08:00
Fedi Bouzazi fb52ba4fa1 target/cortex_m: support DWT version 2.1 for Archv8_M
According to Arm®v8-M Architecture Reference Manual:
section D1.2.59 DWT_DEVARCH, DWT Device Architecture Register,
the field REVISION bits [19:16] defines two DWT architectures revision

Signed-off-by: Fedi Bouzazi <fedi.bouzazi@st.com>
Change-Id: I948dae0710ac921a7f0fbcef3ccacdae99184fe4
Reviewed-on: https://review.openocd.org/c/openocd/+/7800
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-17 12:14:03 +00:00
Daniel Goehring 300fe1d405 target/aarch64: add AArch64 mdd and mwd support
For ARMv8, add AArch64 mdd and mwd support. AArch32 not supported.

Change-Id: I25490471e16943e5a67d7649595d77643aa9a095
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7192
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-09-17 12:07:17 +00:00
Tim Newsome 2c2135a0cb target/riscv: Don't assert in riscv013_get_register()
When the target isn't halted, simply return an error. This used to be
purely internal code so an assert was appropriate. Now after some
refactoring and with unavailable harts you could get here when the hart
is unavailable. In that case the right thing is simply to return an
error message.

Change-Id: I49d26a11fe7565c645fd2480e89a2c35ea9b1688
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-13 13:44:20 -07:00
Tim Newsome fb26f4f89d target/xtensa: Fix build warning.
Change-Id: I9ee69807bec729480dd94da874fe1771d8f06078
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-12 13:11:05 -07:00
Tim Newsome 8c1f1b77d3 Merge commit 'ee31f1578a333a75737bc5b183cd4ae98cdaf798' into from_upstream
Conflicts:
	Makefile.am
	jimtcl
	src/helper/Makefile.am
	src/rtos/rtos.c
	src/rtos/rtos.h
	src/rtos/rtos_standard_stackings.c

Change-Id: I00c98d20089558744988184370a8cb7f95f03329
2023-09-12 12:55:10 -07:00
Tim Newsome 67c2835997
Merge pull request #911 from riscv/from_upstream
From upstream
2023-09-11 12:53:42 -07:00
Marek Vrbka d41a204d82 image: fix binary detection for small files
Previously, if the image file was less than 9 bytes long,
it was assumed to be an error when it could be a binary
image file. This patch makes OpenOCD detect these cases
as binary files.

Change-Id: I5b4dad2b547786246887812ac75907378fe58671
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7880
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-08 22:01:59 +00:00
Marek Vrbka 6f986d2cd7 target: Unify the output of "bp" command
This patch unifies the lines printed by the "bp" command
so that different types of breakpoints are printed in
the same format.

Change-Id: Ic1335eda1c58072a334aed9cf0011431c8ec86a4
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7861
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-09-08 21:58:06 +00:00
Kirill Radkin 022e438292 target: Change policy of removing watchpoints/breakpoints.
Now internal watch/breakpoint will not be removed in case
of error during removing triggers from hardware.

Also change signature of some functions (for deletion
bp/wp) to print message in case of some error.

Change-Id: I71cd1f556a33975005d0ee372fc384fddfddc3bf
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7738
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-09-08 21:57:19 +00:00
Tim Newsome 53f21336c4
Merge pull request #912 from MarekVCodasip/make-unknown-semihosting-error
target/riscv_semihosting: Make the unknown operation number an error
2023-09-08 09:22:10 -07:00
Tim Newsome 42dcc99026
Merge pull request #909 from en-sc/en-sc/cleanup-enumerate-triggers
target/riscv: cleanup riscv_enumerate_triggers()
2023-09-08 09:21:55 -07:00
Evgeniy Naydanov c286f938f4 target/riscv: cleanup riscv_enumerate_triggers()
1. Propagate error codes.
2. Disable leftover triggers in case `tinfo` is supported.

Change-Id: Ie20edb4d8b9245e13ac8757bf6afe549ac99c4f1
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-07 13:39:50 +03:00
Marek Vrbka 1936dbd6cf target/riscv_semihosting: Make the unknown operation number an error
Previously, an unknown semihosting operation number
was logged as debug. This patch changes it and few
other places to be logged as error instead.

Change-Id: I83cae5ca1e3daed440f92b08bd372bfffbbad63c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-07 08:08:06 +02:00
Marek Vrbka 8ad41767c0 target/riscv: Reject size 2 soft breakpoints when C extension not supported
This patch disables software breakpoints of size 2 for targets
which don't support compressed instructions.

Change-Id: I8200b22a51c97ba2aa89e6328beadde8dd35cdd5
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-04 07:47:03 +02:00
Tim Newsome 699eecaab4
Merge pull request #906 from MarekVCodasip/zero-no-cache
target/riscv: Don't write to zero.
2023-08-30 10:59:54 -07:00
Tim Newsome 0801c66ff4 Merge commit 'dfbbfac4d72e247e8094a49c8573b2f49689b6d5' into from_upstream
Change-Id: I6e7c0866291dd87946a4fd49d9bfe4cddefb3957
2023-08-29 13:10:44 -07:00
Tim Newsome 5efea16944
Merge pull request #900 from aap-sc/aap-sc/simplify_state_managment
riscv: simplify state management during examine
2023-08-29 10:11:52 -07:00
Artur Rojek 3b38226370 mips32: add per-cpu quirks feature
Introduce the ability to detect CPUs based on CP0 PRId register and
apply cpu specific quirks, which alter the default ejtag behavior.

First of those is EJTAG_QUIRK_PAD_DRET, which makes sure extra NOPs are
placed after the DRET instruction on exit from debug mode. This fixes
resume behavior on Ingenic JZ4780 SoC.

The proper detection of some (currently unsupported) CPUs becomes quite
complicated, so please consult the following Linux kernel code when
adding new CPUs:
* arch/mips/include/asm/cpu.h
* arch/mips/kernel/cpu-probe.c

Change-Id: I0f413d5096cd43ef346b02cea85024985b7face6
Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7859
Tested-by: jenkins
2023-08-26 11:44:50 +00:00
Karl Palsson 3182a1398a target/cortex_m: Add Realtek Real-M200 and M300
These cores are advertised as M23 and M33 compatible, but are identified
by the Realtek implementor id.  These cores are found on the RTL872xD
family, at least.

Raw CPUIDs:
Real-M200 (KM0): 721cd200
Real-M300 (KM4): 721fd220

Change-Id: I4106ccb7e8c562f98072a71e9e818f57999d664e
Signed-off-by: Karl Palsson <karlp@tweak.au>
Reviewed-on: https://review.openocd.org/c/openocd/+/7846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-08-26 11:39:33 +00:00
Karl Palsson 05ee889155 target/cortex_m: check core implementor field
Presently, we only look at the Part Number field of the CPUID, and
completely ignore the Implmentor field, simply assuming it to be ARM.

Parts have since been found, with different implementors, that use
overlapping part numbers, causing detection to fail.

Expand the "part number" field to be a full implementor+part number,
excluding the revision/patch fields, to make checking more reliable.

Change-Id: Id81774f829104f57a0c105320d0d2e479fa01522
Signed-off-by: Karl Palsson <karlp@tweak.au>
Reviewed-on: https://review.openocd.org/c/openocd/+/7845
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-08-26 11:39:20 +00:00
Marek Vrbka 0b914fe5ae target/riscv: Don't write to zero.
During a previous patch, the ignoring of writes to register zero
was deleted. This patch restores it to the original.

Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-08-25 07:54:59 +02:00
Tim Newsome 928f2b374a
Merge pull request #904 from kr-sc/kr-sc/support-sv57
target/riscv: Add support for Sv57 (and Sv57x4) translation mode
2023-08-23 12:03:21 -07:00
Tim Newsome 7aedb15951
Merge pull request #905 from aap-sc/aap-sc/crash_when_on_vector_tgt_running
fix crash when we try to read vector register on a running target
2023-08-23 12:01:49 -07:00
Tim Newsome 5cb60e3f7d
Merge pull request #903 from wxjstz/riscv
target/riscv: fix execute_fence
2023-08-18 09:32:51 -07:00
Parshintsev Anatoly 198edca6d0 riscv: simplify state management during examine
This also fixes a bug when, after `examine` completion, the target still
has  `unknown` status. To reproduce this one spike, it is enough to do
the following:

---
// make sure spike harts are halted
openocd ... -c init -c 'echo "[targets]"'
---

this behavior is quite dangerous and leads to segfaults in some cases

Change-Id: I13915f7038ad6d0251d56d2d519fbad9a2f13c18
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 15:29:19 +03:00
Parshintsev Anatoly 0ae47ae472 fix crash when we try to read vector register on a running target
Change-Id: I0e140d69faa67f8817310cf18a4db3c581013de2
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 00:18:10 +03:00
Xiang W 373b8f1a89 target/riscv: fix execute_fence
This patch improves the following issues:
1. Makes it compatible with targets with progbufsize == 1.
2. Although exceptions don’t update any registers, but  do end execution
of the progbuf. This will make fence rw, rw impossible to execute.

Change-Id: I2208fd31ec6a7dae6e61c5952f90901568caada6
Signed-off-by: Xiang W <wxjstz@126.com>
2023-08-17 09:05:36 +08:00
Parshintsev Anatoly a8fedebcb4 [riscv] refactor functions that register read/write via progbuf
The motivation for this refactor is to fixup error handling for some
corner cases. These functions attempt to cache S0 register and only then
perform a bunch of extra checks to figure out if the requested register
is valid one in this context. The problem is that there are few corner
cases when _*progbuf functions could receive a GPR as an input. For
example, an abstract read could fail (for whatever reason) leading to
infinite recursion:

````
save S0 -> read S0 -> save S0 -> read S0 -> ...
```

The case described above could be fixed by adding extra sanitity checks,
however I decided to make these functions more modular since I find
self-contained functions easier to read.

Change-Id: I01f57bf474ca45ebb67a30cd4d8fdef21f307c7d
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-15 17:54:00 +03:00
Tim Newsome 9260101307
Merge pull request #899 from en-sc/en-sc/trig-handle-res-not-avlbl
target/riscv: improve error handling in trigger setup
2023-08-14 09:48:03 -07:00
Kirill Radkin 1d2eea0399 target/riscv: Add support for Sv57 translation mode (including second-stage translations)
Also fix Sv48x4 translation mode
2023-08-14 14:33:44 +03:00
Daniel Goehring 307a3ca109 target/aarch64: add missing aarch64_poll() calls
Add missing aarch64_poll() calls to ensure the event
TARGET_EVENT_HALTED is called when necessary.

This is needed with the poller update introduced in commit
95603fae18 ("openocd: revert workarounds for 'expr' syntax change")

Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Change-Id: I6e91f1b6bc1f0d16e6f0eb76fc67d20111e3afd2
Reviewed-on: https://review.openocd.org/c/openocd/+/7737
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-08-12 16:47:14 +00:00
Parshintsev Anatoly 2cd8ebf44d breakpoints: use 64-bit type for watchpoint mask and value
This patch changes data types of watchpoint value and mask to allow for
64-bit values match that some architectures (like RISCV) allow.

In addition this patch fixes the behavior of watchpoint command to
zero-out mask if only data value is provided.

Change-Id: I3c7ec1630f03ea9534ec34c0ebe99e08ea56e7f0
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7840
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-08-08 06:11:01 +00:00
Marek Vrbka bab8b8c9eb register: refactor register_cache_invalidate()
register_cache_invalidate() is written a way which uses
pointer arithmetic, which makes it harder to read. This patch
replaces it with more readable way to iterate over array of
structs.

Change-Id: Ia420f70a3bb6998c690c8c600c71301dca9f9dbf
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7735
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-08-03 20:24:16 +00:00
Evgeniy Naydanov 9b558838b1 target/riscv: improve error handling in trigger setup
Change-Id: I235973a3c44fb3d934925c74ffee47f8bd96de0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-08-03 17:58:16 +03:00
Parshintsev Anatoly bb7852646e add diagnostics for non-implemented data watchpoints
Change-Id: If5031c6d8cea1bfcc34bb65fd766f232498ed7ea
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-02 08:56:19 +03:00
Kirill Radkin 16e4096c00 target: OpenOCD fails with assert during running "reset" command
OpenOCD fails in the presence of inactive/unresponsive cores

I faced with case when inactive core returns 0 while reading dtmcontrol.
This leads to failure on assert: "addrbits != 0" in "dbus_scan".

Also change "read_bits","poll_target" funcs to avoid a lot lines in logs

Change-Id: If852126755317789602b7372c5c5732183fff6c5
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-07-31 19:27:51 +03:00
Tim Newsome c07d9251aa
Merge pull request #884 from riscv/from_upstream
Merge up to a3ed12401 from upstream.
2023-07-31 06:58:52 -07:00
Tomas Vanek a5108240f9 target: fix messages and return values of failed op because not halted
Lot of messages was logged as LOG_WARNING, but the operation failed
immediately. Sometimes no error message was logged at all.
Add missing messages, change warnings to errors.

Sometimes ERROR_TARGET_INVALID was returned. Some command handlers
returned ERROR_OK! Always return ERROR_TARGET_NOT_HALTED.

While on it use LOG_TARGET_ERROR() whenever possible.
Prefix command_print() message with 'Error:' to get closer
to LOG_TARGET_ERROR() variant.

Error message was not added to get() and set() methods of
struct xxx_reg_type - the return value is properly checked and a message
is logged by the caller in case of ERROR_TARGET_NOT_HALTED.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I2fe4187c6025f0038956ab387edbf3f461c69398
Reviewed-on: https://review.openocd.org/c/openocd/+/7819
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-29 05:17:44 +00:00
Mark Zhuang a9f28dafd7 target/riscv: support check dbgbase exist
Change-Id: I0d65bf9b33fb6d10c33f4f038045832594579e58
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 14:31:11 +08:00
Mark Zhuang 80a8aa9e19 target/riscv: support multiple DMs
Support assign DMI address of the debug module by pass
-dbgbase to the target create command

Change-Id: I774c3746567f6e6d77c43a62dea5e9e67bb25770
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:44 +08:00
Mark Zhuang 895185caff target/riscv: add dm layer
prepare for support multiple DMs

Change-Id: Ia313006376e4fa762449343e5522b59d3bfd068a
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:38 +08:00
Marek Vrbka 9036f4003a target/riscv: Add target logging to most logging instances
This patch adds target logging to logging instances where it makes sense.
This is especially useful when debugging multiple targets at once,
such as multicore systems.

Change-Id: Ia9861f3fa0e6e5908b683c2a8280659c3c264395
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-24 08:03:32 +02:00
eolson 218f6c0181 target/riscv: Add null pointer check before right shift for bscan tunneling.
Change-Id: I5d4764c777f33d48705b3e5273eb840c13cfbfb7
Signed-off-by: eolson <erin.olson@seagate.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7814
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-07-22 20:16:11 +00:00
Artemiy Volkov d57b2448ee target/arc: fix off-by-one error in arc_save_context()
While not affecting the function's main purpose, an error has
crept into arc_save_context() that results in logging wrong register
values when the debug level is 3 or more. For instance, when debugging a
trivial program and halting at entry to main, the following values are
printed to the log:

Debug: 2915 2020 arc.c:894 arc_save_context(): Get core register regnum=0,
name=r0, value=0x0000000
...
Debug: 2947 2020 arc.c:894 arc_save_context(): Get core register regnum=60,
name=lp_count, value=0x900002d8
Debug: 2948 2020 arc.c:894 arc_save_context(): Get core register regnum=63,
name=pcl, value=0xffffffff
Debug: 2949 2020 arc.c:909 arc_save_context(): Get aux register regnum=64,
name=pc, value=0x900000b4
Debug: 2950 2020 arc.c:909 arc_save_context(): Get aux register regnum=65,
name=lp_start, value=0x900000bc
Debug: 2951 2020 arc.c:909 arc_save_context(): Get aux register regnum=66,
name=lp_end, value=0x00080801
Debug: 2952 2020 arc.c:909 arc_save_context(): Get aux register regnum=67,
name=status32, value=0xffffffff

After the change, the register contents make much more sense:

Debug: 2923 3934 arc.c:889 arc_save_context(): Get core register regnum=0,
name=r0, value=0x00000000
...
Debug: 2955 3934 arc.c:889 arc_save_context(): Get core register regnum=60,
name=lp_count, value=0x00000000
Debug: 2956 3934 arc.c:889 arc_save_context(): Get core register regnum=63,
name=pcl, value=0x900002d8
Debug: 2957 3934 arc.c:903 arc_save_context(): Get aux register regnum=64,
name=pc, value=0x900002da
Debug: 2958 3934 arc.c:903 arc_save_context(): Get aux register regnum=65,
name=lp_start, value=0x900000b4
Debug: 2959 3934 arc.c:903 arc_save_context(): Get aux register regnum=66,
name=lp_end, value=0x900000bc
Debug: 2960 3934 arc.c:903 arc_save_context(): Get aux register regnum=67,
name=status32, value=0x00080801

While at it, simplify a couple of expressions.

Change-Id: I8f2d79404707fbac4503af45b393ea73f91e6beb
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7765
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-22 20:12:21 +00:00
Erhan Kurubas 617f62a476 target/riscv: fix semantic checker warnings
Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.

Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-20 23:09:06 +02:00
Erhan Kurubas e6f30aef80 src: fix clang15 compiler warnings
Below warnings are fixed.

1- A function declaration without a prototype is deprecated in all
versions of C [-Werror,-Wstrict-prototypes]

2- error: variable set but not used [-Werror,-Wunused-but-set-variable]

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1cf14b8e5e3e732ebc9cacc4b1cb9009276a8ea9
Reviewed-on: https://review.openocd.org/c/openocd/+/7569
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-20 23:09:06 +02:00
Tim Newsome fb284475a8
Merge pull request #878 from en-sc/en-sc/trigg-eq-check
target/riscv: cleanup trigger setup
2023-07-18 09:32:37 -07:00
Evgeniy Naydanov a8f28fdd48 target/riscv: cleanup trigger setup
* Add a warning when eq trigger is setup and it's behavior is different
from other triggers.

* Make eq trigger's behavior consistent with other triggers in case of
length == 1.

* Fix a bug in setting chained triggers (LT, GT case).

* Improve logging.

Change-Id: Id1ed0d11971b8ed875afbb979e6c8a8b51dd3818
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-17 20:41:01 +03:00
Tim Newsome b67b80c6ac
Merge pull request #879 from riscv/power_dance3
target/breakpoints: Clear software breakpoints from available targets
2023-07-17 09:30:41 -07:00
Tim Newsome 814a3b5e7b
Merge pull request #871 from en-sc/en-sc/fix-mdx-err
target/riscv: refactor read_memory_progbuf()
2023-07-17 09:30:11 -07:00
Evgeniy Naydanov 8d660ea98d target/riscv: refactor read_memory_progbuf()
There were a couple of problems with previous implementation:

* Misalligned read would return ERROR_OK and print all zeroes.

* CMDERR_BUSY for abstract access was improperly handled:

According to the spec, no assumptions can be made about DM_DATA*
contents in such a case, but these were considered valid values from
memory.

* A fallback to one element read was implemented when DMI_STATUS_BUSY
occurred during batch reads, even though this can be accounted for.

Change-Id: I09174c61c951b2bb97a529b7f0aa5afaa995179b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-14 22:23:02 +03:00
Erhan Kurubas 698adc0c62 target/espressif: cleanup unused macro definitions
Memory region addresses are not in use for now.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9a2189e956ae59b56245ec914ab16719df857b2d
Reviewed-on: https://review.openocd.org/c/openocd/+/7762
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-14 16:50:24 +00:00
Erhan Kurubas 9fd754ca4d target/espressif: read entry addresses of pre-defined stub functions
Debug stubs functionality provided by ESP IDF allows executing
target function in any address. e.g; esp32_cmd_gcov()

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I56d844e5a862c9bf33fdb991b01abb7a76047ca7
Reviewed-on: https://review.openocd.org/c/openocd/+/7758
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-14 16:47:46 +00:00
Erhan Kurubas 29b02402ff target/esp_xtensa: add xtensa on_halt handler
Right after target halt, some activities needs to be done
such as printing exception reason, disable wdts and reading
debug stubs information.
Missing activities will be submitted in the next patches.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I27aad5614d903f4bd7c8d6dba6bfb0bdb93ed8dc
Reviewed-on: https://review.openocd.org/c/openocd/+/7757
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-14 16:44:26 +00:00
Erhan Kurubas 1a3bd45a61 target/espressif: fix build issue with older gcc versions
Compilation on old gcc 4.8.4 fails:
error: missing braces around initializer [-Werror=missing-braces]

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie8b5747f9e23ba5a82bd7f666846e7286284a338
Reviewed-on: https://review.openocd.org/c/openocd/+/7815
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-07-13 21:37:25 +00:00
Mark Zhuang d5425c253c target/riscv: dynamic allocate memory for hawindow
Change-Id: Id2f1a2568a39eec0a9dd4fe0f155619b11f9d6ba
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-14 00:07:47 +08:00
Mark Zhuang 04d8cfc48c target/riscv: update some macro
1. update RISCV_MAX_HARTS to 2^20 according to SPEC
2. remove RISCV_MAX_REGISTERS, it's not used anywhere anymore
3. add parentheses

Change-Id: Iadf0fa1ba3bbe5b9420b8430883e140db87f4f9e
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-14 00:07:44 +08:00
Tim Newsome 674911ef18 Merge commit 'a3ed12401b1f7d9578fb7da881d3504e07acfc27' into from_upstream
Conflicts:
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c

Change-Id: I65bdb4d28c91e9022ce811de976c9bf474a0b590
2023-07-12 16:32:38 -07:00
Tim Newsome 122c54b4c2 target/riscv: Message when harts become available.
Change-Id: I3824e215a845ba7df3c7887ce1693378fde94b4b
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-12 16:17:43 -07:00
Tim Newsome 39a4f37f84 target/breakpoints: Clear software breakpoints from available targets
If a target where a software breakpoint was set is not currently
available, but there are other targets in the same SMP group that are
available, then we can use those to remove the software breakpoint.

Change-Id: I9faa427c7b3aee31504e6e6599539e6f29b58d8f
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-12 16:17:40 -07:00
Tim Newsome 162cc1e79d target/riscv: Fix typo in gdb_regno_cacheable() comment.
Change-Id: If8806853d47779b5b208202803ed5da437f7b624
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-06 10:40:59 -07:00
Tim Newsome 21d21408aa
Merge pull request #872 from aap-sc/aap-sc/smp_manipulation
[target/riscv] support for smp group manipulation
2023-07-06 09:10:11 -07:00
Marek Vrbka ea115917b9 target/riscv: Fix the trigger writing sequence
According to section 5.6 in the RISC-V debug specification, the previous
way to set triggers was incorrect, as was discussed as part of
https://github.com/riscv/riscv-openocd/issues/870. This commit fixes the
sequence to be in line with the specification as well as adds some comments
to clarify for any future reader as to what is actually done.

Change-Id: Iffc5cc0f866a466a7aaa72a4c53ee95c9080ac9d
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-04 12:04:02 +02:00
Parshintsev Anatoly 2903daa9f1 [target/riscv] support for smp group manipulation
this functionality allows to query if a target belongs to some smp group
and to dynamically turn on/off smp-specific behavior

Change-Id: I469453d95e7c1640a91bc60d80c854404e508535
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-07-03 17:28:40 +03:00
Marek Vrbka 56fd04832a semihosting: fix handling of errno
This patch fixes the handling of errno by setting the sys_errn
only if error has actually occurred during the semihosting call.
It also fixes few issues where error was not set in the first place.

Change-Id: I2fbe562f3ec5e6220b800de04cd33aa1f409c7a0
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7730
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-07-01 17:58:52 +00:00
Marek Vrbka 6ef75352f1 semihosting: improve semihosting opcode debug messages
This patch introduces function semihosting_opcode_to_str() which
converts semihosting opcodes to strings. This function is then
used in debug messages to improve log analysis and troubleshooting.

Change-Id: Iffea49dae13d6a626ae0db40d379cba3c9ea5bd3
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7726
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-07-01 15:03:30 +00:00
Tim Newsome 92c0319261
Merge pull request #873 from eosea/bscan_tunnel_seg_fault_fix
Add null pointer check before right shift for bscan tunneling.
2023-06-29 10:09:12 -07:00
Mark Zhuang 34418ed1c8 target/riscv: fix haltgroup_supported to info->haltgroup_supported
Change-Id: Id1276aecd3097d90e035bf3808e0c472188ba474
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-06-27 15:46:23 +08:00
eolson 9d23d3774a Add null pointer check before right shift for bscan tunneling.
Change-Id: I5d4764c777f33d48705b3e5273eb840c13cfbfb7
Signed-off-by: eolson <erin.olson@seagate.com>
2023-06-22 13:11:15 -05:00
Tim Newsome 470c2a402c
Merge pull request #868 from en-sc/en-sc/upstream-resume-err-2
target/riscv: resume only halted harts
2023-06-21 09:37:40 -07:00
Tim Newsome 1bcabbebb7
Merge pull request #857 from riscv/power_dance2
When dcsr.ebreak* might be cleared, halt the target and set it again
2023-06-21 09:32:23 -07:00
Evgeniy Naydanov 8ca5c2fbe4 target/riscv: resume only halted harts
With this change, failures to resume a hart due to it not being halted
are more explicitly logged or reported as an error.

Change-Id: Ia55d8df85a908363d0f2140637ce1e47c1ab6251
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-06-21 11:44:38 +03:00
Tim Newsome bf07ddef8a target/riscv: From tick(), set ebreak* if necessary.
This involves halting the target, which might have unintended side
effects, but when the debugger is connected software breakpoints must
trap to the debugger. Anything else is a terrible user experience.

Change-Id: I1f7bb610eeeb054cc3042dc6bcfc16589ce12a31
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:59:45 -07:00
Tim Newsome da5bf318b9 target/riscv: Track whether ebreak* is set.
We need to know, so we can set it when necessary.

Change-Id: I1f0d5107f1208f7b9316e15870f0804e51232dee
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:57:49 -07:00
Tim Newsome 87bfe9f505 target/riscv: Add periodic tick() callback
Intended as a place where we can interact with the target without too
much concern about preserving state and doing exactly the right thing
while poll() is going on.

Change-Id: Ic9bd441caae85901a131fd45e742599803df89b5
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:57:49 -07:00
Tim Newsome 34f9ff0d0d target/riscv: Add some event callbacks.
Specifically, call into the RISC-V version when target becomes halted,
running, or unavailable.

I'll be using unavailable shortly.

Change-Id: I9ffffdccbf22e053fe6390d656b362bf9ab9559a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:57:44 -07:00
Tim Newsome 6e64b685f4 target/riscv: Track whether halt groups are supported.
Will be used later when we want to do a quick halt/resume.

Change-Id: Ib80166234c4c277b7d9ce26b7566ac0f93017e64
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:31 -07:00
Tim Newsome b496bebcda target/riscv: Improve update_dcsr()->set_dcsr_ebreak()
* Only set ebreak bits that might be supported based on misa.
* Don't write dcsr if its value wouldn't change.

Change-Id: I7087af0b0df0fbdbf994373b5c887b9b389df872
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 9d8bbb559d target/riscv: Tweak set_group().
Make it callable earlier, handle `supported` being NULL, and make enum
names more clear.

Change-Id: If4d286b54ccfc01eb5de5a57eb18f748c920e979
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 866282ba9e target/riscv: Add debug msg to reset_delays_wait
Makes it easier when reading debug logs.

Change-Id: I3938437357e0d74e1cda680693f907a20c5579c7
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 2a64da39b0 target/riscv: Remove unused riscv013_on_halt function
The riscv013_on_halt function was being called but its implementation was
empty, providing no additional functionality. Removed the function declaration,
calls to it, and its implementation since it is not required.

Change-Id: I425ea890deadeec945f0a47af247f3f99172e801
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Marek Vrbka eebcf3cff1 riscv/semihosting: Fix ebreak skip on fileio mode
This patch fixes skipping the semihosting sequence if
the fileio mode is enabled on riscv. This change was
tested by me and is in the riscv-openocd fork for a year now.

Original merge request:
https://github.com/riscv/riscv-openocd/pull/699

Original author: Wu Zhigang
zhigang.wu@starfivetech.com
https://github.com/wzgpeter

Change-Id: Iadaa0a48d1f82d3a7ca168f8a6b656ff6ab78e03
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7729
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2023-06-16 22:11:51 +00:00
Tim Newsome ebfd43c84f target/riscv: Early exit magic sequence checks in riscv_semihosting
When halted we don't need to read all 3 instructions before deciding the
sequence doesn't match.

Change-Id: I9f8345960ce27e859265af901a368166a70b9fde
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-15 10:40:37 -07:00
Marek Vrbka 9f23a1d7c1 semihosting: fix non-zero value on Windows isatty()
On Windows, isatty() can return any non-zero value if it's an interactive
device. Which diverges from the ARM semihosting specification. This patch
introduces a fix to make the SYS_ISTTY operation conform to spec.

Change-Id: I9bc4f3cb82370812825d52419851910b3e3f35cc
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7725
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-06-10 17:10:27 +00:00
Marek Vrbka 0854c83076 gdb_server: add debug signal reason prints
Added debug prints to show what is the target debug reason. Also added
debug print for Ctrl-C response. This is useful for troubleshooting and
log analysis.

Change-Id: I055936257d989efe7255656198a8d73a367fcd15
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7720
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-06-10 17:00:26 +00:00
Tim Newsome 166b68c1b0 target/riscv: Remove unnecessary prototypes.
These functions used to exist but don't anymore. (Pointed out in #863)

Change-Id: Iac6b5edd320bdff7628a788861e332f956dcd93d
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-09 15:13:44 -07:00
Tim Newsome 973c72887c
Merge pull request #860 from riscv/examine_state
target/riscv: set_dcsr_ebreak() while target->state is still changed
2023-06-08 09:10:55 -07:00
Tim Newsome ad89d570e7 target/riscv: set_dcsr_ebreak() while target->state is still changed
Otherwise it fails.

Fixes #859.

Change-Id: Ib59e6d840316b881481a9b1e01f9d546e73bf932
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-07 09:49:58 -07:00
Marek Vrbka 711ac4f0f0 target/riscv: add register cache flushing and invalidation to protobuf execution.
Previously, progbuf execution did not flush or invalidate the register cache which could lead to incorrect behavior. This patch fixes it as well as refactors few sore points in the code related to it.

Change-Id: I353b931ca70a1828d4a9cc512aead00441730875
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-06-07 09:41:30 +02:00
Tim Newsome 0ab2ebd191 target/riscv: Select hart in update_dcsr()
Otherwise we may end up modifying DCSR of a different hart than
intended.

Change-Id: I39bde21a1444623ed150f2b3d504b9318b9d6191
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-05 09:39:14 -07:00
Erhan Kurubas 4dc4280555 target/espressif: fix clang scan-build warning
Clang reports that 3rd function call argument is an uninitialized value
file esp32_apptrace.c line:1270

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I73e254d4eb0c6b3152229717d8827d334784ab92
Reviewed-on: https://review.openocd.org/c/openocd/+/7719
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-06-02 21:00:32 +00:00
Bohdan Tymkiv 72131e05e9 cortex_m: fix reading of DCB_DSCSR register
Value in the 'dscsr' variable is garbage until the DAP queue is run.
Postpone evaluation of the 'secure_state' variable. Reading the
core registers in between will execute the DAP queue.

Change-Id: I44959e882dbafb1b9779e813c3d13f3b3dbcd47f
Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7693
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-06-02 20:57:49 +00:00
Antonio Borneo 4a57f3ebb2 target: armv8: fix support of pointer authentication
The registers pauth_dmask and pauth_cmask are not accessible in
AARCH32 mode. Tagging them as 'hidden' is not enough and triggers
error:
	Failed to read pauth_dmask register
while halting the core.

Tag the pauth registers as not existing, unless required by user.

Note: for non existing registers there should be no need to
      allocate their register cache. Let's keep this for a further
      improvement.

Change-Id: Iaa0d006a3d8ee611ee93333ed49a8615a6c94276
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: d0436b0cda ("armv8: Add support of pointer authentication")
Reviewed-on: https://review.openocd.org/c/openocd/+/7712
Tested-by: jenkins
Reviewed-by: Koudai Iwahori <koudai@google.com>
2023-06-02 20:57:05 +00:00
Tim Newsome 5a9654d272
Merge pull request #854 from en-sc/en-sc/fix-regacc-running
target/riscv: fix register access on running target
2023-06-02 08:25:07 -07:00
Evgeniy Naydanov 3a29542056 target/riscv: fix register access on running target
Register access on running target should fail if mstatus needs to be
modified.

Change-Id: Iec8e8d514ef2f5ca42606a5534cce55aaaa99180
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-31 22:22:53 +03:00
Ian Thompson 2dd34cbe0b target/xtensa: add file-IO support
- Manual integration of File-IO support from xt0.2 release
- Verified with applications linked using gdbio LSP
- No new clang static analysis warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: Iedc5f885b2548097ef4f11ae1a675b5944f5fdf0
Reviewed-on: https://review.openocd.org/c/openocd/+/7550
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-27 06:43:59 +00:00
Antonio Borneo 8297836170 jtag: rewrite jim_jtag_tap_enabler() as COMMAND_HANDLER
The function is used for commands:
- jtag tapisenabled
- jtag tapenable
- jtag tapdisable

While there, add the missing .help and .usage fields and fix the
incorrect check in jtag_tap_enable() and jtag_tap_disable().

Change-Id: I0e1c9f0b8d9fbad19d09610a97498bec8003c27e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7554
Tested-by: jenkins
2023-05-27 06:42:51 +00:00
Antonio Borneo 5dd047fbbe jtag: rewrite commands 'jtag newtap' and 'swd newdap' as COMMAND_HANDLER
While there:
- fix memory leak in case of error on values tap->chip,
  tap->tapname, tap->expected_ids;
- check for out of memory error;
- fix minor coding style issue;
- add the missing .usage field;
- remove functions not in use anymore.

Change-Id: I1c8c3ffeb324e9eacb919c7e0d94fd72122c9a81
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7431
Tested-by: jenkins
2023-05-27 06:42:01 +00:00
Antonio Borneo da76f8f0b4 target: use unsigned int for timeout_ms
Change the prototype of functions:
- target_run_algorithm()
- target_wait_algorithm()
- target_wait_state()
- struct target_type::run_algorithm()
- struct target_type::wait_algorithm()
to use unsigned int for timeout_ms instead of int.
Change accordingly the variables passed as parameter.

Change-Id: I0b8d6e691bb3c749eeb2911dc5a86c38cc0cb65d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7562
Tested-by: jenkins
2023-05-27 06:41:17 +00:00
Antonio Borneo fe6befbd80 target: rewrite command 'arp_waitstate' as COMMAND_HANDLER
While there, add the missing .usage field and remove the now
unused function jim_target_tap_disabled().

Change-Id: I79afcc5097643fc264354c6c3957786a55f40498
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7561
Tested-by: jenkins
2023-05-27 06:40:40 +00:00
Antonio Borneo 22ababc12e target: rewrite command 'arp_examine' as COMMAND_HANDLER
Change-Id: I8f227b219ca39f198e1e39847ddd36bb9880a328
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7560
Tested-by: jenkins
2023-05-27 06:40:16 +00:00
Antonio Borneo 0f0a4b1452 target: espressif: apptrace: declare a local function as static
The function esp32_cmd_apptrace_generic() is not used outside the
file.

Declare it as static.
Detected through 'sparse' tool.

Change-Id: I08c6b92fb01594320bc3ae6b16067ac4eb51ca12
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7676
Tested-by: jenkins
2023-05-27 06:39:35 +00:00
Erhan Kurubas a0fecd6c41 target/espressif: add system level tracing feature
Produces traces compatible with SEGGER SystemView tool.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: If1057309edbb91ed2cf1ebf9137c378d3deb9b88
Reviewed-on: https://review.openocd.org/c/openocd/+/7606
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-27 06:38:51 +00:00
Antonio Borneo 144d940a8b Revert "target/image: zero-initialize ELF segments up to p_memsz"
This reverts commit 047b1a8fc2.

Commit 047b1a8fc2 ("target/image: zero-initialize ELF segments
up to p_memsz") breaks the backward compatibility introducing some
problem:
- an empty bss segment with paddr in SRAM gets zero filled at load
  but does not survive after a reset, causing verify to fail;
- an empty bss segment with paddr in FLASH causes excessive flash
  usage, which can exceed flash size (causing error) and makes
  flash aging faster.

Revert it while looking for a better implementation.

Change-Id: Iaaf926dafce46a220a5bbe20c8576eb449996d76
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7658
Reviewed-by: Bohdan Tymkiv <bohdan200@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Peter Collingbourne <pcc@google.com>
Tested-by: jenkins
2023-05-27 06:38:12 +00:00
Tim Newsome f0898155d1 target/riscv: Set dcsr.ebreak* during examine()
This way if you connect to a running target, before it's hit a breakpoint,
then when it does hit the breakpoint OpenOCD will catch it.

Change-Id: I6f1e5f169fa385f46759015786e664693c3872e4
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:01:47 -07:00
Tim Newsome 21433e83ee target: poll() failure does not mean the target halted.
Poll failure just means poll failed. It's safer to assume the target is
still running, because then if it is running and subsequently halts we can
relay this to gdb correctly. We can't do the other way around, because once
gdb thinks the target has halted, it can't deal with it spontaneously
running.

Change-Id: Idb56137f1d6baa9afc1b0e55e4a48f407b8ebe83
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Tim Newsome 82ed02f92a target/riscv: Always clear progbuf cache in examine().
When a DM was powered down, we end up in examine() again, and clearly if
the DM was powered down we need to invalidate that cache.

Change-Id: I5eb6a289939f313e06c09cac22245db083026aa3
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Tim Newsome 1c5cf8023c target/riscv: Reset DTM when it reports an error.
The error state is sticky, so this has to be done to recover.

Change-Id: I589f3cdab0f2351fd25f89951830cbc16c39bd93
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Amaury Pouly 5924d9f30c target/riscv-013: clear sticky error when DMI operation fails
When a DMI operation does not succeed (either because of a timeout
or an error), the specification says that the error in the `op`
field is sticky and needs to cleared by writing `dmireset` in `dtmcs`.
This is already done for timeouts in increase_dmi_busy_delay
but not for errors.

Change-Id: I7c5f27a5cf145511a1a8b64a45a586521e1cbe41
Signed-off-by: Amaury Pouly <amaury.pouly@lowrisc.org>
Reviewed-on: https://review.openocd.org/c/openocd/+/7688
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-05-25 16:19:12 +00:00
Evgeniy Naydanov 5a29a7399f target/riscv: refactor register accesses
Change-Id: I45731d501f6261c4142c70afacf3fbbe42cf2806
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-23 20:20:19 +03:00
Evgeniy Naydanov c822dc8194 target/riscv: improve register caching (prep_*, cleanup_*)
Introduce riscv_write_register to prep_for_register/vector_access and
cleanup_after_register/vector_access.

Change-Id: I77a0a06ac6f12eceec309f0aff94aa77bd56ff55
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 8f3a617dc7 target/riscv: improve register caching (riscv_write_register)
This commit introduces a new function, which can be used to reduce number
of register accesses.

Change-Id: I125809726eb7797b11121175c3ad66bedb66dd0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 7a181e8bbc target/riscv: use `riscv_reg_t` and `enum gbb_regno` consistently
Change-Id: Ia476251e835fa5fd129ae6b679c6049c5c60c716
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 919a98a05b target/riscv: fix register cache flushing
Since writing a register can make some GPRs dirty (e.g. S0, S1), registers
should be flushed in reverse order, so GPRs are flushed last.

Change-Id: Ice352a4df4ae064619c0f9905db634a7b57e4711
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Tim Newsome 461eb65e21
Merge pull request #847 from riscv/data1_cache
target/riscv: Comment that data1 might change.
2023-05-18 10:56:00 -07:00
Antonio Borneo fb34eeb442 target: arm_adi_v5: move in include file the declaration of dap_ops
The struct containing SWD and JTAG operations are declared as
extern in the C file.

Mode them in include file arm_adi_v5.h to silent 'sparse' error
for global variable definition without declaration in an include
file.

Change-Id: I59088512c052d5a120c38404a882ed512a68ca02
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7675
Tested-by: jenkins
2023-05-18 10:16:12 +00:00
Antonio Borneo d5c177cd3d server: gdb: export gdb_actual_connections through a function
The internal variable 'gdb_actual_connections' is used by log and
by semihosting to determine if there are active GDB connections.

Keep the variable local in server's code and only export its value
through a dedicated function.

This solves the issue detected by 'parse' of the variable defined
as global but not declared in any include file.

Change-Id: I6e14f4cb1097787404094636f8a2a291340222dd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7673
Tested-by: jenkins
2023-05-18 10:14:56 +00:00
Antonio Borneo d15f58ad4c target: arm_dpm: with pointers, use NULL instead of 0
Don't assign pointer to 0, use NULL.

Detected through 'sparse' tool.

Change-Id: I34551112ddab9dedf8537c8111d32356c170e7d5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7669
Tested-by: jenkins
2023-05-18 10:11:53 +00:00
Antonio Borneo ed46188a72 target: move in target_type.h the target_type's declaration
The static analyser 'sparse' complains, while compiling a target's
file, that the struct target_type is declared in the file as non
static, but it is not exposed through an include file.
The message is:
	warning: symbol 'XXX' was not declared. Should it be static?

Move the list of target_type's declaration in target_type.h
While there, fix a name clash in stm8.c

Change-Id: Ia9c681e0825cfd04d509616dbc04a0cf4944f379
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7659
Tested-by: jenkins
2023-05-18 09:54:59 +00:00
Tim Newsome be5187d0a8 target/riscv: Comment that data1 might change.
In case in the future I have the same idea of optimizing progbuf writes
again.

Change-Id: Ie383487691cceeff75e2c22f4c85fc1fe4873937
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-17 09:46:23 -07:00
Tim Newsome d78d991191
Merge pull request #850 from riscv/cleanup-in-target-c
Minor cleanup in target.c
2023-05-16 09:27:57 -07:00
Tim Newsome 15bd33cc20
Merge pull request #844 from riscv/from_upstream
Merge 228fe7 from upstream
2023-05-15 08:17:31 -07:00
Jan Matyas bd275ef483 Minor cleanup in target.c
Small cleanup in target.c to get rid of few upstream differences:

- removed a pointless check for `reg->exists` - already checked
  few lines above
- unify one log message with what's in upstream

Change-Id: I3fd761157382670611fa90de84e2dfc90192f473
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-05-15 15:09:55 +02:00
Antonio Borneo 85b5c51806 target: rewrite command 'arp_reset' as COMMAND_HANDLER
While there, add the missing .usage field and move in target.c the
enum nvp_assert.

Change-Id: Ia4f2f962887b5a35faeaa4eae128fa2865569b24
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7559
Tested-by: jenkins
2023-05-13 08:55:55 +00:00
Antonio Borneo b931286ab4 target: rewrite command 'arp_halt' as COMMAND_HANDLER
While there, add the missing .usage field.

Change-Id: I748382cafe08443c458ff1d4e47819610cfbf85c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7558
Tested-by: jenkins
2023-05-13 08:55:14 +00:00
Antonio Borneo 219412f9d6 target: rewrite command 'arp_poll' as COMMAND_HANDLER
While there, add the missing .usage field.

Change-Id: I16e0aeacdaaada09fa77ad29552fa4025eff0c45
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7557
Tested-by: jenkins
2023-05-13 08:54:37 +00:00
Antonio Borneo 599f1cf763 openocd: trivial replace of jim-nvp with new nvp
For some trivial case only, replace calls to jim-nvp with calls
to the new OpenOCD nvp.

Change-Id: Ifd9aff32b67748af8ab808e6a6b6e64f5271b888
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7553
Tested-by: jenkins
2023-05-13 08:49:05 +00:00
Antonio Borneo 160288137a xtensa: fix build with gcc 13.1.1
New gcc does not understand that the variable 'restore_ms' is set
to 'true' only when the variable 'ms' is assigned in
	static int xtensa_write_dirty_registers(...)
	{
		xtensa_reg_val_t ms;
		bool restore_ms = false;
		...
		if (...) {
			ms = regval;
			restore_ms = true;
			...
		}
		...
		if (restore_ms) {
			USE(ms);
		}
		...
	}
and complains about possible use of uninitialized variable 'ms'.

Sadly initialize 'ms' to zero to hide this false positive.

Change-Id: I1fb3949070c8abbf4aa45a740f0ca2fdb753d4fa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7681
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Tested-by: jenkins
2023-05-13 08:47:27 +00:00
Tim Newsome 57d20e4d96 target/riscv: Remove non-functional code in riscv_program_exec().
Addresses #845.

Change-Id: If4eee383f92946669a84f92e52a3ac3600707525
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-10 16:58:09 -07:00
Antonio Borneo 329b10754a target: etm: fix check trace status
Current code tests a function pointer against a numeric value that
is the same enum type as returned by the pointed function.
Clearly the author was willing to call the function and check its
returned value.

Fix the check by calling the function.

Detected through 'sparse' tool.

Change-Id: I27d18d26c2c797160a397daa32835c199014b70b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Checkpatch-ignore: GIT_COMMIT_ID
Fixes: 237e894805 ("reworked etm/etb into a generic etm part with trace capture")
Reviewed-on: https://review.openocd.org/c/openocd/+/7599
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-05-06 13:34:32 +00:00
Antonio Borneo d771d7f1a7 target: with pointers, use NULL instead of 0
Don't assign pointer to 0, use NULL.
Don't pass 0 ad pointer argument, pass NULL.

Detected through 'sparse' tool.

Change-Id: I806031d2ae505fa5f0accc6be1936d48cd365ca4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7604
Tested-by: jenkins
2023-05-05 22:14:29 +00:00
Antonio Borneo 4b7dc55738 target: rtt: include rtt.h
Let source file to include its file .h to validate the exported
prototypes.

Detected through 'sparse' tool.

Change-Id: I8ae2f8f1fdaea5683e157247463533b17237e464
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7602
Tested-by: jenkins
2023-05-05 22:14:11 +00:00
Antonio Borneo ea62f8e22a target: use 'ULL' suffix for long constants
On 32 bit hosts, gcc should consider constants without suffix as
32 bits values.

Use the suffix 'ULL' to guarantee it is a 64 bit.

Detected through 'sparse' tool.

Change-Id: I205ca986968fef9a536f87492d1f6c80e41829f3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7601
Tested-by: jenkins
2023-05-05 22:10:18 +00:00
Tim Newsome da44fb5407 Merge commit '228fe7300c7df7aa05ba2c0bc19edde6d0156401' into from_upstream
Conflicts:
	doc/openocd.texi
	src/jtag/aice/aice_pipe.c
	src/jtag/aice/aice_usb.c
	src/rtos/FreeRTOS.c
	src/rtos/hwthread.c
	src/rtos/rtos_standard_stackings.c
	src/target/riscv/riscv.c

Change-Id: I0c6228c499d60274325be895fbcd8007ed1699bc
2023-05-04 14:38:10 -07:00
Tim Newsome 80d529cad3
Merge pull request #843 from riscv/hypervisor_translate
target/riscv: Support hypervisor address translation
2023-05-04 09:52:54 -07:00
Antonio Borneo 8670ad4caa target/espressif: fix clang report on list use
It looks like a false positive.
Scan-build considers as possible to:
- have list_empty() return false;
- list_for_each_safe() to not execute any loop, thus not assigning
  a non-NULL value to 'block';
- the NULL pointer 'block' is passed to list_del().
This is not possible because with list_empty(), the loop runs at
least once.

Rewrite the function to simplify the code and making it easier for
scan-build to check it.

This also drops an incorrect use of list_for_each_safe(), where
the 'safe' version was not required.

Change-Id: Ia8b1d221cf9df73db1196e3f51986023dcaf78eb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 8d1dcf293a ("target/espressif: add application tracing functionality over JTAG")
Reviewed-on: https://review.openocd.org/c/openocd/+/7608
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
2023-04-30 14:52:36 +00:00
Antonio Borneo c1dc7935f7 target/espressif: fix clang report on use of garbage value
When the function xtensa_queue_dbg_reg_read() returns error, the
array 'tmp' remains not initialized and scan-build complains while
computing buf_get_u32() that:
	Result of operation is garbage or undefined

Check the returned value of xtensa_queue_dbg_reg_read() and
propagate it.

Change-Id: If0aaad068b97ef0a76560e262d16429afd469585
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 8d1dcf293a ("target/espressif: add application tracing functionality over JTAG")
Reviewed-on: https://review.openocd.org/c/openocd/+/7607
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-04-30 14:52:18 +00:00
Erhan Kurubas bb073f897c src: fix clang15 compiler warnings
Below warnings are fixed.

1- A function declaration without a prototype is deprecated in all
versions of C [-Werror,-Wstrict-prototypes]

2- error: variable set but not used [-Werror,-Wunused-but-set-variable]

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1cf14b8e5e3e732ebc9cacc4b1cb9009276a8ea9
Reviewed-on: https://review.openocd.org/c/openocd/+/7569
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-04-30 14:51:42 +00:00
Julien Massot 2096afc1b0 aarch64: Add support for ARMv8-R
ARMv8-R platforms are similar to ARMv8-A regarding
JTAG and most cpu registers. ARMv8-R doesn't has MMU
but has MPU instead.

ARMv8-R platforms can be AArch32 only such as Cortex-R52,
or AArch64 capable like Cortex-R82.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ib086f71685d1e3704b396d478ae9399dd8a391e1
Reviewed-on: https://review.openocd.org/c/openocd/+/6843
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-30 14:46:25 +00:00
Julien Massot 0bb0056abc target:armv8: aarch32 do not try to restore same EL
While debugging a Cortex-R52 OpenOCD fail to restore context
on line
retval = dpm->instr_write_data_r0(dpm,
		ARMV8_MSR_GP_xPSR_T1(1, 0, 15), cpsr);

which trigger this exception:

aarch64.c:1206 aarch64_restore_context(): r8a779a0.r52
armv8_dpm.c:560 armv8_dpm_modeswitch(): restoring mode, cpsr = 0x0000011f
1262753 armv8_dpm.c:598 armv8_dpm_modeswitch(): target_el = 1, last_el = 1
armv8_dpm.c:611 armv8_dpm_modeswitch(): SPSR = 0x0000011f
armv8_dpm.c:260 dpmv8_exec_opcode(): Opcode 0x8f00f390, DSCR.ERR=1, DSCR.EL=1

and finally OpenOCD doesn't succeed to restore the processor.

This check 'dpm->last_el != target_el' exist for aarch64,
so might be correct for aarch32 too.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: I41d1006233251dcaf6d69bda580488b204b7eb63
Reviewed-on: https://review.openocd.org/c/openocd/+/6807
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-30 14:44:52 +00:00
Tim Newsome 880fa0a8da target/riscv: Support VS-stage and G-stage address translation.
These are used in hypervisor mode.

Change-Id: I5f773816f73c83b4ae57727fbc3b36b65b6185eb
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-28 14:48:49 -07:00
Tim Newsome fc52bfefc8
Merge pull request #840 from aap-sc/aap-sc/resume_on_bp
fix bp handling during resume
2023-04-28 09:13:58 -07:00
Parshintsev Anatoly 152ef1a936 fix bp handling during resume
Depending client parameters OpenOCD resume command can do step+resume
to avoid triggering a pending breakpoint

Change-Id: Ib7ae544e1a1f13843584f4c1c87db17851642b89
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-04-27 10:06:08 +03:00
Tim Newsome d4429f62e4 target/riscv: Refactor to create riscv_effective_privilege_mode()
Change-Id: I65bba63a7bde746b0069133f8a42529d1d857d3e
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-25 10:58:24 -07:00
Tim Newsome 5da1e086b6 target/riscv: Move some code from riscv_address_translate() to riscv_virt2phys()
Also minor code cleanups, and better debug messages.

Change-Id: Iffc9951c8b38da2e3516926108b93db91883680e
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-25 10:35:12 -07:00
Tim Newsome 85f44fc37f Comment pte_shift
Change-Id: I48ad7637ff37898ca2df0f48501cf2c72fa1e722
2023-04-25 09:34:27 -07:00
Tim Newsome f2c2ebbcd0 target/riscv: Add constants for vsatp, hgatp
Change-Id: I130a8f7a7abc294bbdf60e7e0ce0bccb72bf920a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-25 09:30:27 -07:00
Parshintsev Anatoly 7ca8350d3a target/riscv: respect error code from dm013_select_target in select_prepped_harts
Change-Id: I3099589521538590e366d60629e49cfc74e2d0c6
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-04-24 21:15:56 +03:00
Erhan Kurubas 8d1dcf293a target/espressif: add application tracing functionality over JTAG
This feature allows to transfer arbitrary data between host and
ESP32 via JTAG.

The main use cases:

1- Collecting application specific data
2- Lightweight logging to the host
3- System behaviour analysis with SEGGER SystemView
4- Source code coverage

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I95dee00ac22891fa326915a3fcac3c088cbb2afc
Reviewed-on: https://review.openocd.org/c/openocd/+/7163
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-14 15:15:54 +00:00
Tim Newsome c454db3eee
Merge pull request #835 from en-sc/en-sc/fix-err-resume
target/riscv: Handle error code in resume_prep
2023-04-11 09:54:47 -07:00
Tim Newsome da229508aa
Merge pull request #833 from zqb-all/read_log128
target/riscv: support log memory access128 for read
2023-04-11 09:53:48 -07:00
Evgeniy Naydanov 08df077083 target/riscv: Handle error code in resume_prep
If hart can't change pc (e.g. it is running), resume command should
fail.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I14627366d574d806ea16262b7d305d8161f8bcc2
2023-04-10 17:19:20 +03:00
Mark Zhuang aa7344225b target/riscv: support log memory access128 for read
Change-Id: I9235150fa00c03a1d75d0b44a7500758daa56e2b
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-04-10 09:48:48 +08:00
François LEGAL 55e04e3157 src/target/mips_m4k : add fast read method
Add the fast read method to speed up flash verification
after programming. Works the same as fast write already
implemented.

Signed-off-by: François LEGAL <devel@thom.fr.eu.org>
Change-Id: I74611a3542a88212f0483ec8ee368aba3d1f03c7
Reviewed-on: https://review.openocd.org/c/openocd/+/7564
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-07 21:46:36 +00:00
François LEGAL 18aacc8bf3 src/target/mips_m4k : fix condition on overlapping workspace data area
The condition to check if the workspace area (used by actual MIPS code
executed on target) and data area (sandbox to put data to be read/written
to/from flash) is wrong, thus preventing the use of FAST_* commands to
program/verify FLASH.

Signed-off-by: François LEGAL <devel@thom.fr.eu.org>
Change-Id: Ic68424b7f42d44e550433a120093db5e7980fd56
Reviewed-on: https://review.openocd.org/c/openocd/+/7563
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-04-07 21:45:18 +00:00
Tim Newsome 0c76e263e3
Merge pull request #823 from panciyan/riscv
target/riscv: leaf PTE check PTE_W missing
2023-04-07 10:05:57 -07:00
Tim Newsome 15bb3e23b8
Merge pull request #821 from en-sc/en-sc/fix-reset-mharts
target/riscv: simplify reset for rtos harts
2023-04-06 09:54:15 -07:00
Tim Newsome 52b102318b
Merge pull request #830 from zqb-all/csr_32bit
target/riscv: set some csr size to 32
2023-04-06 09:40:59 -07:00
Tim Newsome 7e36bb6158
Merge branch 'riscv' into hypervisor
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-05 10:48:56 -07:00
Evgeniy Naydanov 1c168242e9 target/riscv: simplify reset
Since the deletion of `-rtos hwthread`, there is no need to treat harts
with `-rtos` specified differently on reset.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I88a9129936b5172bb7479dfa1255e29ff460c054
2023-04-05 19:14:45 +03:00
Tim Newsome c6ba4166e4
Merge pull request #816 from riscv/from_upstream
Merge up to commit '1293ddd65713d6551775b67169387622ada477c1' from upstream
2023-04-05 08:47:27 -07:00
Tim Newsome 2dc14117a7
Merge pull request #819 from zqb-all/fix_size_assert
target/riscv: support log memory access128
2023-04-04 11:05:52 -07:00
Mark Zhuang e284aa066e target/riscv: set some csr size to 32
Change-Id: I4703b7b8ad492b14dc8d188ebb8f645c568fd515
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-04-03 23:53:14 +08:00
Tim Newsome 38cf11abab
Merge pull request #824 from riscv/aia
target/riscv: AIA regs, check for H not V
2023-03-29 13:52:34 -07:00
Tim Newsome 4fdcc14e26 target/riscv: Set hypervisor bits.
No other attempt is made at doing anything hypervisor-specific. Are
other things necessary?

Change-Id: Ib65f114888840cf0878f9bfe028c9a42b436aa3f
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-29 13:40:39 -07:00
Antonio Borneo e9a7221b68 target: rewrite command 'target smp' as COMMAND_HANDLER
This also fixes an incorrect return ERROR_xx from a jim command,
propagated from return value of rtos_smp_init().

Change-Id: Icf4893c00aabd8fadd60077c5e8a2e926f687518
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7511
Tested-by: jenkins
2023-03-25 18:16:02 +00:00
Antonio Borneo 12b405a4ac target: rewrite command 'target names' as COMMAND_HANDLER
Print one entry per line.
While there add the mandatory 'usage' field.

Change-Id: Ia832684817f3bdbfa4cb943cd97e3f9fb2605902
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7510
Tested-by: jenkins
2023-03-25 18:15:53 +00:00
Antonio Borneo d9d698103e target: rewrite command 'target types' as COMMAND_HANDLER
Print one entry per line.
While there add the mandatory 'usage' field.

Change-Id: I135556e12154e33fdbd0f71d89f6fe37c69813b7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7509
Tested-by: jenkins
2023-03-25 18:15:43 +00:00
Antonio Borneo 26f457896c target: rewrite command 'target current' as COMMAND_HANDLER
While there add the mandatory 'usage' field.

Change-Id: I3e5b826ca58f7ade30a443ada0cb4a9cd9ea35c2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7508
Tested-by: jenkins
2023-03-25 18:15:33 +00:00
Antonio Borneo 583efa68f7 target: rewrite command 'arp_halt_gdb' as COMMAND_HANDLER
While there add the mandatory 'usage' field.

Change-Id: I5389881dac25877dc32930ec36ee546e48ecc14d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7507
Tested-by: jenkins
2023-03-25 18:15:23 +00:00
Antonio Borneo 2dda0e37d9 target: rewrite command 'examine_deferred' as COMMAND_HANDLER
Check for empty command line, add the mandatory 'usage' field.

Change-Id: I9c3606242ec3dda9026fe19222162a110e618bff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7506
Tested-by: jenkins
2023-03-25 18:15:14 +00:00
Antonio Borneo cca64798f8 target: rewrite command 'was_examined' as COMMAND_HANDLER
Check for empty command line, add the mandatory 'usage' field.

Change-Id: I3f59448458fe01268bf5f4293aea5adcbd6d8279
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7505
Tested-by: jenkins
2023-03-25 18:15:03 +00:00
Antonio Borneo 113ba58231 target: rewrite command 'target curstate' as COMMAND_HANDLER
While there, add the mandatory 'usage' field.

Change-Id: Ibfda6f56a1450e2eb9ad3092d756de0778f4a092
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7504
Tested-by: jenkins
2023-03-25 18:14:52 +00:00
Antonio Borneo 584986ab1c target: rewrite command 'read_memory' as COMMAND_HANDLER
While there, fix typo on 'exceeds'.
In a following patch, the output could be formatted and split in N
values per line to make it easier to read by humans.

Change-Id: I295111a80934393011e46311f6cf6c13f2bdc0a3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7503
Tested-by: jenkins
2023-03-25 18:14:40 +00:00
Antonio Borneo 6f8c27dcfc target: arm_tpiu_swo: rewrite command 'tpiu init' as COMMAND_HANDLER
Change-Id: Iaaccfc62dd85267066a152c434f254d1b9a0c4f1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7502
Tested-by: jenkins
2023-03-25 18:14:30 +00:00
Antonio Borneo 90ddac12e3 target: arm_tpiu_swo: rewrite command 'tpiu names' as COMMAND_HANDLER
While there, format in a human readable way the output list by
using one line per tpiu name.

Change-Id: I937c92b6c1e92509cf8aa96be1517a51bc363600
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7501
Tested-by: jenkins
2023-03-25 18:14:18 +00:00
Antonio Borneo 5d39a8852a target: arm_tpiu_swo: rewrite command 'tpiu enable' as COMMAND_HANDLER
Change-Id: Ia600948b99a229ef0490b7f576df62f880db8546
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7500
Tested-by: jenkins
2023-03-25 18:14:07 +00:00
Antonio Borneo 8fa6db6e8e target: arm_tpiu_swo: rewrite command 'tpiu disable' as COMMAND_HANDLER
Change-Id: I689482f898bde2afa2881b2f311676a6b98abb9a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7499
Tested-by: jenkins
2023-03-25 18:13:56 +00:00
Antonio Borneo f76e67a440 target: arm_dap: rewrite command 'dap names' as COMMAND_HANDLER
While there, format in a human readable way the output list by
using one line per dap name.

Change-Id: I24a47350105b90db15808c61790f05d807120739
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7498
Tested-by: jenkins
2023-03-25 18:13:46 +00:00
Antonio Borneo 5da4ef25c8 target: cti: rewrite command 'cti names' as COMMAND_HANDLER
While there, format in a human readable way the output list by
using one line per cti name.

Change-Id: I6d4870ee512fe7e6935d73355c2377ad805ccc3b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7492
Tested-by: jenkins
2023-03-25 18:12:20 +00:00
Antonio Borneo c4f2337d02 target: armv4_5: rewrite commands 'arm mcr/mrc' as COMMAND_HANDLER
While there, add a check for target halted and check the number of
parameters accordingly to the command name.

Change-Id: I9e8bb109c35039561997d14782fac682267aee65
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7491
Tested-by: jenkins
2023-03-25 18:12:02 +00:00
Antonio Borneo 21e6252965 target: aarch64: rewrite commands 'aarch64 mcr/mrc' as COMMAND_HANDLER
This also fixes an incorrect return ERROR_TARGET_NOT_HALTED from a
jim command.

Change-Id: I99a02a21bedb64e60944e295c7cf24356e07be60
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7490
Tested-by: jenkins
2023-03-25 18:11:26 +00:00
Tomas Vanek 415715d91a target/adi_v5_jtag: fix endianness error in transaction replay
The code for JTAG WAIT recovery did not handle DP_SELECT
endianness.

While on it, mark missing ADIv6 DP SELECT1 handling as TODO.

Change-Id: I44f3bc8fc9fd2483c0293b6d4f2c51a60ca01873
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7540
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-25 18:07:51 +00:00
Tomas Vanek 6ecd99ff9b target/adi_v5_swd: update comment about SWD capability
The multidrop SWD is also supported.

Change-Id: I9fefc54fc9d40a75194285cd6e0f10c5c347d9b6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7537
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-25 18:07:04 +00:00
Erhan Kurubas faeae51d7f target/espressif: check common_magic instead of gdb_arch string
The value returned by target_get_gdb_arch() is something specific for GDB.
There could be several variants of the same CPU.
If we start implementing all the variants, checking the string value,
could become incorrect.
It's better to check for xtensa->common_magic == XTENSA_COMMON_MAGIC

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I20f3fdced176c3b9ab00f889743161ecad7280f9
Reviewed-on: https://review.openocd.org/c/openocd/+/7536
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-25 18:06:36 +00:00
Mark Zhuang dfce1d2708 target/riscv: [NFC] rename variables named read/write
read/write is system function

Change-Id: I75db4dd5a1c60e9cff8a58a863a887beffc37cab
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-25 21:18:12 +08:00
Mark Zhuang 4cccda353c target/riscv: support log memory access128
Change-Id: I6b22c97f81fac26703b66d3dbd8b6d41aaea4875
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-25 20:31:42 +08:00
Tim Newsome 5bc9c207eb target/riscv: Don't ignore maskmax for icount.
Icount triggers don't have a maskmax field at all. This is a cut and
paste error.

Change-Id: I001b3d41bf683599706dba713f7be475e8dd1668
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-24 13:41:06 -07:00
Tim Newsome 194a90186c target/riscv: AIA regs, check for H not V
Change-Id: Iac37b79dc737fd64a21dce83b3ef36f1a8aae118
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-24 09:21:48 -07:00
panciyan 1479eca38f target/riscv: leaf PTE check PTE_W missing
When permission bits R, W, and X in PTE all three are zero,
the PTE is a pointter to the next level of the page table;
otherwise, it is a leaf PTE. Here PTE_W is missed.

Change-Id: I82a4cc4e64280f0fcad75b20e51b617520aff29b
Signed-off-by: panciyan <panciyan@eswincomputing.com>
2023-03-23 02:45:42 +00:00
Tim Newsome d744207943
Merge pull request #815 from riscv/s_aia
target/riscv: Expose S?aia CSRs if they're on the target.
2023-03-20 08:45:13 -07:00
Ian Thompson 904d58c208 target/xtensa: add NX support
- Manual integration of NX support from xt0.2 release
- No new clang static analysis warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I95b51ccc83e56c0d4dbf09e01969ed6a4a93d497
Reviewed-on: https://review.openocd.org/c/openocd/+/7356
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-18 21:56:50 +00:00
Peter Collingbourne 047b1a8fc2 target/image: zero-initialize ELF segments up to p_memsz
We were previously not zero-initializing ELF segments between p_filesz
and p_memsz (aka BSS). However, this may be necessary depending on the
user's application. Therefore, start doing so.

Change-Id: I5a743390069583aca7ee276f53afeccf2cac0855
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7513
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-18 21:52:02 +00:00
Tim Newsome 2cd3436002 Fix build.
Change-Id: I89de7dc21d7958531ec9619905d3d8c4f54a3acf
2023-03-16 18:08:25 -07:00
Tim Newsome 868ebdd89c Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream
This includes
https://sourceforge.net/p/openocd/mailman/message/37710818/, which
should fix #814.

Conflicts:
	.travis.yml
	contrib/loaders/flash/stm32/stm32f1x.S
	contrib/loaders/flash/stm32/stm32f2x.S
	doc/openocd.texi
	src/rtos/FreeRTOS.c
	src/server/gdb_server.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg
	tcl/target/gd32vf103.cfg
	tools/scripts/checkpatch.pl

Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
2023-03-16 18:02:35 -07:00
Tim Newsome 3387015af0
Merge pull request #800 from en-sc/en-sc/try-all-trigs-in-maybe-add-trig
Try all triggers in maybe_add_trigger_t*
2023-03-16 16:58:12 -07:00
Tim Newsome 2c760b6317 Expose S?aia CSRs if they're on the target.
Untested, because I don't have a target that implements this.

Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-16 15:37:06 -07:00
Tim Newsome eb8cabf821 Update encoding.h.
Change-Id: I1b6d2cac86ec485310761b73370fb2667ebb3bbd
2023-03-16 11:27:06 -07:00
Tim Newsome 750f7b4bc3
Merge pull request #812 from XuHangHub/riscv
target/riscv: fix the bug of using S2 register in read_memory_progbuf
2023-03-15 09:29:03 -07:00
Evgeniy Naydanov 55a576037e Try all triggers in maybe_add_trigger_t2 and _t6
It is possible for triggers of the same type to support different match
field values, so it is needed to try all the triggers, not just the
first one.

Fixes issue #788.

Signed-off-by: Evgeniy Naydanov evgeniy.naydanov@syntacore.com
Change-Id: I4c9fbc98bae7259377456d9ad8e770232724a592
2023-03-15 13:05:33 +03:00
Hang Xu 2370d78249 target/riscv: fix the bug of using S2 register in read_memory_progbuf
We should avoid using x16~x31 register in program buffer because there
are no such general purpose registers in RVE(Embedded) extension.
For targets that support rvE, when the parameter increment=0
and count>1 of the read_memory_progbuf function, openocd will cause
an error due to the use of the s2 register.
For example:
{Command} {riscv repeat_read} count address [size=4]

Change-Id: I8b74dcc15cd00a400f2f1354c577a82132394435
Signed-off-by: Hang Xu <xuhang@eswincomputing.com>
2023-03-12 04:01:05 +00:00
Tim Newsome dcb0b5b976 target/riscv: Remove unused address_in variable.
Change-Id: Iead46b543a3b866f36b4d61a8824b6335dab276a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-10 10:58:46 -08:00
Tim Newsome 4f97898889 Merge commit 'd1b882f2c014258be5397067e45848fa5465b78b' into from_upstream
Conflicts:
	doc/openocd.texi
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c

Change-Id: I8cd557a10c3d5beeaed05ecc05d4c325a9ee7e70
2023-02-28 10:54:48 -08:00