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target/riscv: Don't write to zero. 

During a previous patch, the ignoring of writes to register zero
was deleted. This patch restores it to the original.

Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
This commit is contained in:
Marek Vrbka 2023-08-21 13:49:43 +02:00
parent 5cb60e3f7d
commit 0b914fe5ae
1 changed files with 3 additions and 0 deletions
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3
src/target/riscv/riscv.c
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@ -4718,6 +4718,9 @@ unsigned int riscv_count_harts(struct target *target)
*/
static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write)
{
if (regno == GDB_REGNO_ZERO)
return !is_write;
/* GPRs, FPRs, vector registers are just normal data stores. */
if (regno <= GDB_REGNO_XPR31 ||
(regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||