Merge pull request #903 from wxjstz/riscv
target/riscv: fix execute_fence
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commit
5cb60e3f7d
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@ -2920,15 +2920,35 @@ static int execute_fence(struct target *target)
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/* FIXME: For non-coherent systems we need to flush the caches right
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* here, but there's no ISA-defined way of doing that. */
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int result;
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struct riscv_program program;
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riscv_program_init(&program, target);
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riscv_program_fence_i(&program);
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riscv_program_fence_rw_rw(&program);
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int result = riscv_program_exec(&program, target);
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if (result != ERROR_OK)
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LOG_TARGET_DEBUG(target, "Unable to execute pre-fence");
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return ERROR_OK;
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if (has_sufficient_progbuf(target, 3)) {
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riscv_program_init(&program, target);
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riscv_program_fence_rw_rw(&program);
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riscv_program_fence_i(&program);
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result = riscv_program_exec(&program, target);
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if (result != ERROR_OK)
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LOG_TARGET_DEBUG(target, "Unable to execute pre-fence");
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return ERROR_OK;
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}
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if (has_sufficient_progbuf(target, 2)) {
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riscv_program_init(&program, target);
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riscv_program_fence_i(&program);
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result = riscv_program_exec(&program, target);
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if (result != ERROR_OK)
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LOG_TARGET_DEBUG(target, "Unable to execute fence.i");
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riscv_program_init(&program, target);
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riscv_program_fence_rw_rw(&program);
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result = riscv_program_exec(&program, target);
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if (result != ERROR_OK)
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LOG_TARGET_DEBUG(target, "Unable to execute fence rw, rw");
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return ERROR_OK;
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}
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return ERROR_FAIL;
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}
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static void log_memory_access128(target_addr_t address, uint64_t value_h,
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@ -5070,7 +5090,7 @@ void riscv013_fill_dm_nop_u64(struct target *target, char *buf)
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static int maybe_execute_fence_i(struct target *target)
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{
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if (has_sufficient_progbuf(target, 3))
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if (has_sufficient_progbuf(target, 2))
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return execute_fence(target);
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return ERROR_OK;
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}
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