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Merge pull request #906 from MarekVCodasip/zero-no-cache 

target/riscv: Don't write to zero.
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Tim Newsome 2023-08-30 10:59:54 -07:00 committed by GitHub
parent 5efea16944 0b914fe5ae
commit 699eecaab4
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src/target/riscv/riscv.c
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@ -4753,6 +4753,9 @@ unsigned int riscv_count_harts(struct target *target)
*/
static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write)
{
if (regno == GDB_REGNO_ZERO)
return !is_write;
/* GPRs, FPRs, vector registers are just normal data stores. */
if (regno <= GDB_REGNO_XPR31 ||
(regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||