target/riscv: Stop caching writes to DPC

Since DPC is WARL (same rules as MEPC according to
the specification), it is possible that
writes to it won't result in the exact value present.
Therefore, writes to it shouldn't be cached, same as
with other WARL registers.

Change-Id: I818c0cef9727b999b7d84b19f9f42cd706c99d69
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>

src/target/riscv/riscv.c

@@ -4960,8 +4960,6 @@ static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write)
 	 * CSRs. */
 	switch (regno) {
 		case GDB_REGNO_DPC:
-			return true;
-
 		case GDB_REGNO_VSTART:
 		case GDB_REGNO_VXSAT:
 		case GDB_REGNO_VXRM: