xtensa: update XDM register map for TRAX support
- Include additional debug module registers - Add translation function for DM reg addr -> ID - Add DM read/write commands Signed-off-by: ianst <ianst@cadence.com> Change-Id: If95419d24a9f27a40fa695c8c15326cdfd127ef1 Reviewed-on: https://review.openocd.org/c/openocd/+/7973 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
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ianst
Antonio Borneo
parent
9ebc2a6519
commit
f8096ce687
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@ -11487,6 +11487,12 @@ Execute arbitrary instruction(s) provided as an ascii string. The string repres
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number of instruction bytes, thus its length must be even.
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@end deffn
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@deffn {Command} {xtensa dm} (address) [value]
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Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads
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and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified
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only for write accesses.
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@end deffn
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@subsection Xtensa Performance Monitor Configuration
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@deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
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@ -3978,6 +3978,38 @@ COMMAND_HANDLER(xtensa_cmd_smpbreak)
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get_current_target(CMD_CTX));
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}
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COMMAND_HELPER(xtensa_cmd_dm_rw_do, struct xtensa *xtensa)
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{
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if (CMD_ARGC == 1) {
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// read: xtensa dm addr
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uint32_t addr = strtoul(CMD_ARGV[0], NULL, 0);
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uint32_t val;
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int res = xtensa_dm_read(&xtensa->dbg_mod, addr, &val);
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if (res == ERROR_OK)
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command_print(CMD, "xtensa DM(0x%08" PRIx32 ") -> 0x%08" PRIx32, addr, val);
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else
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command_print(CMD, "xtensa DM(0x%08" PRIx32 ") : read ERROR %" PRId32, addr, res);
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return res;
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} else if (CMD_ARGC == 2) {
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// write: xtensa dm addr value
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uint32_t addr = strtoul(CMD_ARGV[0], NULL, 0);
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uint32_t val = strtoul(CMD_ARGV[1], NULL, 0);
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int res = xtensa_dm_write(&xtensa->dbg_mod, addr, val);
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if (res == ERROR_OK)
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command_print(CMD, "xtensa DM(0x%08" PRIx32 ") <- 0x%08" PRIx32, addr, val);
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else
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command_print(CMD, "xtensa DM(0x%08" PRIx32 ") : write ERROR %" PRId32, addr, res);
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return res;
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}
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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COMMAND_HANDLER(xtensa_cmd_dm_rw)
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{
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return CALL_COMMAND_HANDLER(xtensa_cmd_dm_rw_do,
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target_to_xtensa(get_current_target(CMD_CTX)));
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}
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COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa)
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{
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struct xtensa_trace_status trace_status;
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@ -4234,6 +4266,13 @@ static const struct command_registration xtensa_any_command_handlers[] = {
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.help = "Set the way the CPU chains OCD breaks",
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.usage = "[none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]",
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},
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{
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.name = "dm",
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.handler = xtensa_cmd_dm_rw,
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.mode = COMMAND_ANY,
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.help = "Xtensa DM read/write",
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.usage = "addr [value]"
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},
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{
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.name = "perfmon_enable",
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.handler = xtensa_cmd_perfmon_enable,
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@ -34,6 +34,16 @@ static const struct xtensa_dm_pwr_reg_offsets xdm_pwr_regs[XDMREG_PWRNUM] =
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static const struct xtensa_dm_reg_offsets xdm_regs[XDMREG_NUM] =
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XTENSA_DM_REG_OFFSETS;
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static enum xtensa_dm_reg xtensa_dm_regaddr_to_id(uint32_t addr)
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{
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enum xtensa_dm_reg id;
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uint32_t addr_masked = (addr & (XTENSA_DM_APB_ALIGN - 1));
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for (id = XDMREG_TRAXID; id < XDMREG_NUM; id++)
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if (xdm_regs[id].apb == addr_masked)
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break;
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return id;
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}
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static void xtensa_dm_add_set_ir(struct xtensa_debug_module *dm, uint8_t value)
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{
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struct scan_field field;
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@ -285,6 +295,34 @@ int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bit
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return xtensa_dm_queue_execute(dm);
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}
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int xtensa_dm_read(struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val)
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{
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enum xtensa_dm_reg reg = xtensa_dm_regaddr_to_id(addr);
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uint8_t buf[sizeof(uint32_t)];
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if (reg < XDMREG_NUM) {
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xtensa_dm_queue_enable(dm);
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dm->dbg_ops->queue_reg_read(dm, reg, buf);
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xtensa_dm_queue_tdi_idle(dm);
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int res = xtensa_dm_queue_execute(dm);
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if (res == ERROR_OK && val)
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*val = buf_get_u32(buf, 0, 32);
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return res;
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}
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return ERROR_FAIL;
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}
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int xtensa_dm_write(struct xtensa_debug_module *dm, uint32_t addr, uint32_t val)
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{
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enum xtensa_dm_reg reg = xtensa_dm_regaddr_to_id(addr);
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if (reg < XDMREG_NUM) {
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xtensa_dm_queue_enable(dm);
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dm->dbg_ops->queue_reg_write(dm, reg, val);
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xtensa_dm_queue_tdi_idle(dm);
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return xtensa_dm_queue_execute(dm);
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}
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return ERROR_FAIL;
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}
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int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
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{
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/*Turn off trace unit so we can start a new trace. */
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@ -75,6 +75,22 @@ enum xtensa_dm_reg {
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XDMREG_DELAYCNT,
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XDMREG_MEMADDRSTART,
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XDMREG_MEMADDREND,
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XDMREG_EXTTIMELO,
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XDMREG_EXTTIMEHI,
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XDMREG_TRAXRSVD48,
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XDMREG_TRAXRSVD4C,
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XDMREG_TRAXRSVD50,
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XDMREG_TRAXRSVD54,
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XDMREG_TRAXRSVD58,
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XDMREG_TRAXRSVD5C,
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XDMREG_TRAXRSVD60,
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XDMREG_TRAXRSVD64,
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XDMREG_TRAXRSVD68,
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XDMREG_TRAXRSVD6C,
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XDMREG_TRAXRSVD70,
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XDMREG_TRAXRSVD74,
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XDMREG_CONFIGID0,
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XDMREG_CONFIGID1,
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/* Performance Monitor Registers */
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XDMREG_PMG,
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@ -168,6 +184,22 @@ struct xtensa_dm_reg_offsets {
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{ .nar = 0x07, .apb = 0x001c }, /* XDMREG_DELAYCNT */ \
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{ .nar = 0x08, .apb = 0x0020 }, /* XDMREG_MEMADDRSTART */ \
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{ .nar = 0x09, .apb = 0x0024 }, /* XDMREG_MEMADDREND */ \
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{ .nar = 0x10, .apb = 0x0040 }, /* XDMREG_EXTTIMELO */ \
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{ .nar = 0x11, .apb = 0x0044 }, /* XDMREG_EXTTIMEHI */ \
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{ .nar = 0x12, .apb = 0x0048 }, /* XDMREG_TRAXRSVD48 */ \
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{ .nar = 0x13, .apb = 0x004c }, /* XDMREG_TRAXRSVD4C */ \
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{ .nar = 0x14, .apb = 0x0050 }, /* XDMREG_TRAXRSVD50 */ \
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{ .nar = 0x15, .apb = 0x0054 }, /* XDMREG_TRAXRSVD54 */ \
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{ .nar = 0x16, .apb = 0x0058 }, /* XDMREG_TRAXRSVD58 */ \
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{ .nar = 0x17, .apb = 0x005c }, /* XDMREG_TRAXRSVD5C */ \
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{ .nar = 0x18, .apb = 0x0060 }, /* XDMREG_TRAXRSVD60 */ \
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{ .nar = 0x19, .apb = 0x0064 }, /* XDMREG_TRAXRSVD64 */ \
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{ .nar = 0x1a, .apb = 0x0068 }, /* XDMREG_TRAXRSVD68 */ \
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{ .nar = 0x1b, .apb = 0x006c }, /* XDMREG_TRAXRSVD6C */ \
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{ .nar = 0x1c, .apb = 0x0070 }, /* XDMREG_TRAXRSVD70 */ \
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{ .nar = 0x1d, .apb = 0x0074 }, /* XDMREG_TRAXRSVD74 */ \
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{ .nar = 0x1e, .apb = 0x0078 }, /* XDMREG_CONFIGID0 */ \
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{ .nar = 0x1f, .apb = 0x007c }, /* XDMREG_CONFIGID1 */ \
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\
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/* Performance Monitor Registers */ \
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{ .nar = 0x20, .apb = 0x1000 }, /* XDMREG_PMG */ \
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@ -297,6 +329,11 @@ struct xtensa_dm_reg_offsets {
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#define DEBUGCAUSE_DI BIT(5) /* Debug Interrupt */
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#define DEBUGCAUSE_VALID BIT(31) /* Pseudo-value to trigger reread (NX only) */
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/* TRAXID */
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#define TRAXID_PRODNO_TRAX 0 /* TRAXID.PRODNO value for TRAX module */
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#define TRAXID_PRODNO_SHIFT 28
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#define TRAXID_PRODNO_MASK 0xf
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#define TRAXCTRL_TREN BIT(0) /* Trace enable. Tracing starts on 0->1 */
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#define TRAXCTRL_TRSTP BIT(1) /* Trace Stop. Make 1 to stop trace. */
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#define TRAXCTRL_PCMEN BIT(2) /* PC match enable */
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@ -512,6 +549,9 @@ static inline xtensa_dsr_t xtensa_dm_core_status_get(struct xtensa_debug_module
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return dm->core_status.dsr;
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}
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int xtensa_dm_read(struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val);
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int xtensa_dm_write(struct xtensa_debug_module *dm, uint32_t addr, uint32_t val);
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int xtensa_dm_device_id_read(struct xtensa_debug_module *dm);
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static inline xtensa_ocdid_t xtensa_dm_device_id_get(struct xtensa_debug_module *dm)
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{
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