Clifford Wolf
|
924d9d6e86
|
Added read-enable to memory model
|
2015-09-25 12:23:11 +02:00 |
Clifford Wolf
|
84bf862f7c
|
Spell check (by Larry Doolittle)
|
2015-08-14 10:56:05 +02:00 |
Clifford Wolf
|
8d6d5c30d9
|
Added WORDS parameter to $meminit
|
2015-07-31 10:40:09 +02:00 |
Clifford Wolf
|
6c84341f22
|
Fixed trailing whitespaces
|
2015-07-02 11:14:30 +02:00 |
Clifford Wolf
|
422794c584
|
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
|
2015-03-01 11:20:22 +01:00 |
Clifford Wolf
|
1f1deda888
|
Added non-std verilog assume() statement
|
2015-02-26 18:47:39 +01:00 |
Clifford Wolf
|
c2ba4fb2fd
|
Convert floating point cell parameters to strings
|
2015-02-18 23:35:23 +01:00 |
Clifford Wolf
|
e9368a1d7e
|
Various fixes for memories with offsets
|
2015-02-14 14:21:15 +01:00 |
Clifford Wolf
|
a8e9d37c14
|
Creating $meminit cells in verilog front-end
|
2015-02-14 10:49:30 +01:00 |
Clifford Wolf
|
234a45a3d5
|
Ignore explicit assignments to constants in HDL code
|
2015-02-08 00:58:03 +01:00 |
Clifford Wolf
|
c8305e3a6d
|
Fixed a bug with autowire bit size
(removed leftover from when we tried to auto-size the wires)
|
2015-02-08 00:48:23 +01:00 |
Clifford Wolf
|
eefe78be09
|
Fixed memory->start_offset handling
|
2015-01-01 12:56:01 +01:00 |
Clifford Wolf
|
137f35373f
|
Changed more code to dict<> and pool<>
|
2014-12-28 19:24:24 +01:00 |
Clifford Wolf
|
edb3c9d0c4
|
Renamed extend() to extend_xx(), changed most users to extend_u0()
|
2014-12-24 09:51:17 +01:00 |
Clifford Wolf
|
fe829bdbdc
|
Added log_warning() API
|
2014-11-09 10:44:23 +01:00 |
Clifford Wolf
|
4569a747f8
|
Renamed SIZE() to GetSize() because of name collision on Win32
|
2014-10-10 17:07:24 +02:00 |
Clifford Wolf
|
deff416ea7
|
Fixed assignment of out-of bounds array element
|
2014-09-06 17:58:27 +02:00 |
Clifford Wolf
|
8927aa6148
|
Removed $bu0 cell type
|
2014-09-04 02:07:52 +02:00 |
Clifford Wolf
|
7bfc4ae120
|
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
|
2014-08-21 12:43:51 +02:00 |
Clifford Wolf
|
64713647a9
|
Improved AST ProcessGenerator performance
|
2014-08-17 02:17:49 +02:00 |
Clifford Wolf
|
d491fd8c19
|
Use stackmap<> in AST ProcessGenerator
|
2014-08-17 00:57:24 +02:00 |
Clifford Wolf
|
83e2698e10
|
AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
|
2014-08-16 19:31:59 +02:00 |
Clifford Wolf
|
978a933b6a
|
Added RTLIL::SigSpec::to_sigbit_map()
|
2014-08-14 23:14:47 +02:00 |
Clifford Wolf
|
c83b990458
|
Changed the AST genWidthRTLIL subst interface to use a std::map
|
2014-08-14 23:02:07 +02:00 |
Clifford Wolf
|
b9bd22b8c8
|
More cleanups related to RTLIL::IdString usage
|
2014-08-02 13:19:57 +02:00 |
Clifford Wolf
|
cdae8abe16
|
Renamed port access function on RTLIL::Cell, added param access functions
|
2014-07-31 16:38:54 +02:00 |
Clifford Wolf
|
1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
|
2014-07-31 13:19:47 +02:00 |
Clifford Wolf
|
397b00252d
|
Added $shift and $shiftx cell types (needed for correct part select behavior)
|
2014-07-29 16:35:13 +02:00 |
Clifford Wolf
|
48822e79a3
|
Removed left over debug code
|
2014-07-28 19:38:30 +02:00 |
Clifford Wolf
|
ec58965967
|
Fixed part selects of parameters
|
2014-07-28 19:24:28 +02:00 |
Clifford Wolf
|
a03297a7df
|
Set results of out-of-bounds static bit/part select to undef
|
2014-07-28 16:09:50 +02:00 |
Clifford Wolf
|
55521c085a
|
Fixed RTLIL code generator for part select of parameter
|
2014-07-28 15:31:19 +02:00 |
Clifford Wolf
|
0598bc8708
|
Fixed width detection for part selects
|
2014-07-28 15:19:34 +02:00 |
Clifford Wolf
|
27a872d1e7
|
Added support for "upto" wires to Verilog front- and back-end
|
2014-07-28 14:25:03 +02:00 |
Clifford Wolf
|
3c45277ee0
|
Added wire->upto flag for signals such as "wire [0:7] x;"
|
2014-07-28 12:12:13 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
ee65dea738
|
Fixed signdness detection of expressions with bit- and part-selects
|
2014-07-28 10:10:08 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
Clifford Wolf
|
f8fdc47d33
|
Manual fixes for new cell connections API
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
2bec47a404
|
Use only module->addCell() and module->remove() to create and delete cells
|
2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
6aa792c864
|
Replaced more old SigChunk programming patterns
|
2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
c094c53de8
|
Removed RTLIL::SigSpec::optimize()
|
2014-07-23 20:32:28 +02:00 |
Clifford Wolf
|
115dd959d9
|
SigSpec refactoring: More cleanups of old SigSpec use pattern
|
2014-07-22 23:50:21 +02:00 |
Clifford Wolf
|
28b3fd05fa
|
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
|
2014-07-22 20:58:44 +02:00 |
Clifford Wolf
|
7bffde6abd
|
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
|
2014-07-22 20:39:38 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
543551b80a
|
changes in verilog frontend for new $mem/$memwr WR_EN interface
|
2014-07-16 12:49:50 +02:00 |
Clifford Wolf
|
4fc43d1932
|
More found_real-related fixes to AstNode::detectSignWidthWorker
|
2014-06-24 15:08:48 +02:00 |
Clifford Wolf
|
65b2e9c064
|
fixed signdness detection for expressions with reals
|
2014-06-21 21:41:13 +02:00 |
Clifford Wolf
|
5bfe865cec
|
Added found_real feature to AstNode::detectSignWidth
|
2014-06-16 15:00:57 +02:00 |
Clifford Wolf
|
149fe83a8d
|
improved (fixed) conversion of real values to bit vectors
|
2014-06-14 21:00:51 +02:00 |
Clifford Wolf
|
9dd16fa41c
|
Added real->int convertion in ast genrtlil
|
2014-06-14 07:44:19 +02:00 |
Clifford Wolf
|
7c8a7b2131
|
further improved const function support
|
2014-06-07 00:02:05 +02:00 |
Clifford Wolf
|
76da2fe172
|
improved const function support
|
2014-06-06 22:55:02 +02:00 |
Clifford Wolf
|
ae5032af84
|
Fixed bit-extending in $mux argument (use $bu0 instead of $pos)
|
2014-02-26 21:32:19 +01:00 |
Clifford Wolf
|
6bc94b7eb2
|
Don't blow up constants unneccessarily in Verilog frontend
|
2014-02-24 12:41:25 +01:00 |
Clifford Wolf
|
02e6f2c5be
|
Added Verilog support for "`default_nettype none"
|
2014-02-17 14:28:52 +01:00 |
Clifford Wolf
|
5e39e6ece2
|
Correctly convert constants to RTLIL (fixed undef handling)
|
2014-02-15 15:42:10 +01:00 |
Clifford Wolf
|
534c1a5dd0
|
Created basic support for function calls in parameter values
|
2014-02-14 19:56:44 +01:00 |
Clifford Wolf
|
a6750b3753
|
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
|
2014-02-03 13:01:45 +01:00 |
Clifford Wolf
|
d06258f74f
|
Added constant size expression support of sized constants
|
2014-02-01 13:50:23 +01:00 |
Clifford Wolf
|
375c4dddc1
|
Added read_verilog -icells option
|
2014-01-29 00:59:28 +01:00 |
Clifford Wolf
|
1e67099b77
|
Added $assert cell
|
2014-01-19 14:03:40 +01:00 |
Clifford Wolf
|
fb2bf934dc
|
Added correct handling of $memwr priority
|
2014-01-03 00:22:17 +01:00 |
Clifford Wolf
|
369bf81a70
|
Added support for non-const === and !== (for miter circuits)
|
2013-12-27 14:20:15 +01:00 |
Clifford Wolf
|
ecc30255ba
|
Added proper === and !== support in constant expressions
|
2013-12-27 13:50:08 +01:00 |
Clifford Wolf
|
4a4a3fc337
|
Various improvements in support for generate statements
|
2013-12-04 21:06:54 +01:00 |
Clifford Wolf
|
f4b46ed31e
|
Replaced signed_parameters API with CONST_FLAG_SIGNED
|
2013-12-04 14:24:44 +01:00 |
Clifford Wolf
|
93a70959f3
|
Replaced RTLIL::Const::str with generic decoder method
|
2013-12-04 14:14:05 +01:00 |
Clifford Wolf
|
507c63d112
|
Added support for local regs in named blocks
|
2013-12-04 09:10:16 +01:00 |
Clifford Wolf
|
10aa08dca1
|
Fixed temp net name generation in rtlil process generator for abbreviated name matching
|
2013-11-28 21:47:08 +01:00 |
Clifford Wolf
|
0e52f3fa01
|
Added "src" attribute to processes
|
2013-11-28 17:37:50 +01:00 |
Clifford Wolf
|
8dafecd34d
|
Added module->avail_parameters (for advanced techmap features)
|
2013-11-24 20:29:07 +01:00 |
Clifford Wolf
|
f71e27dbf1
|
Remove auto_wire framework (smarter than the verilog standard)
|
2013-11-24 17:29:11 +01:00 |
Clifford Wolf
|
609caa23b5
|
Implemented correct handling of signed module parameters
|
2013-11-24 17:17:21 +01:00 |
Clifford Wolf
|
09471846c5
|
Major improvements in mem2reg and added "init" sync rules
|
2013-11-21 13:49:00 +01:00 |
Clifford Wolf
|
2a25e3bca3
|
Fixed parsing of default cases when not last case
|
2013-11-18 16:10:50 +01:00 |
Clifford Wolf
|
e5b974fa2a
|
Cleanups and bugfixes in response to new internal cell checker
|
2013-11-11 00:39:45 +01:00 |
Clifford Wolf
|
259cc1391e
|
More undef-propagation related fixes
|
2013-11-08 11:40:36 +01:00 |
Clifford Wolf
|
fc6dc0d7b8
|
Fixed handling of power operator
|
2013-11-07 22:20:00 +01:00 |
Clifford Wolf
|
d7cb62ac96
|
Fixed more extend vs. extend_u0 issues
|
2013-11-07 19:20:20 +01:00 |
Clifford Wolf
|
947bd9b96b
|
Renamed extend_un0() to extend_u0() and use it in genrtlil
|
2013-11-07 18:17:10 +01:00 |
Clifford Wolf
|
83a8b8b5ca
|
Fixed const folding in corner cases with parameters
|
2013-11-07 14:08:53 +01:00 |
Clifford Wolf
|
b52bf379b9
|
Fixed width detection for replicate operator
|
2013-11-07 12:43:04 +01:00 |
Clifford Wolf
|
f050c40519
|
Various fixes for correct parameter support
|
2013-11-07 10:02:11 +01:00 |
Clifford Wolf
|
160adccca2
|
Fixed the fix for propagation of width hints for $signed() and $unsigned()
|
2013-11-07 03:01:28 +01:00 |
Clifford Wolf
|
7fe13faefa
|
Fixed propagation of width hints for $signed() and $unsigned()
|
2013-11-06 22:41:21 +01:00 |
Clifford Wolf
|
baeca48a24
|
Additional fixes for undef propagation in concat and replicate ops
|
2013-11-06 21:16:54 +01:00 |
Clifford Wolf
|
6fcbc79b5c
|
Improved width extension with regard to undef propagation
|
2013-11-06 21:05:11 +01:00 |
Clifford Wolf
|
472117d532
|
further improved early width and sign detection in ast simplifier
|
2013-11-04 06:04:42 +01:00 |
Clifford Wolf
|
d2b083f5cb
|
Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
|
2013-11-03 18:56:45 +01:00 |
Clifford Wolf
|
ada80545fa
|
Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
|
2013-11-02 21:13:01 +01:00 |
Clifford Wolf
|
943329c1dc
|
Various ast changes for early expression width detection (prep for constfold fixes)
|
2013-11-02 13:00:17 +01:00 |
Clifford Wolf
|
23cf23418c
|
Fixed handling of boolean attributes (frontends)
|
2013-10-24 11:20:13 +02:00 |
Clifford Wolf
|
0003743432
|
Fixed width and sign detection for ** operator
|
2013-08-19 20:58:01 +02:00 |
Clifford Wolf
|
759852914d
|
Added support for "2**n" shifter encoding
|
2013-08-12 14:47:50 +02:00 |