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Commit Graph

57 Commits

Author SHA1 Message Date
Eddie Hung e17f3f8c63 Consistency 2020-01-17 16:06:20 -08:00
Eddie Hung 4985318263 ice40_dsp: add default values for parameters 2020-01-17 15:37:52 -08:00
Eddie Hung 6692e5d558 ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs 2020-01-17 15:28:02 -08:00
Eddie Hung cd8a640989 Reject if (* init *) present 2019-09-25 18:21:08 -07:00
Eddie Hung 486dd7c483 unextend only used in init 2019-09-25 14:05:59 -07:00
Eddie Hung 53817b8575 Use new port/param overload in pmg 2019-09-20 14:21:22 -07:00
Eddie Hung 1b892ca1be Cleanup ice40_dsp.pmg 2019-09-20 12:03:45 -07:00
Eddie Hung a0d3ecf8c6 Small cleanup 2019-09-20 08:41:28 -07:00
Eddie Hung 8cfcaf108e Disable support for SB_MAC16 reset since it is async 2019-09-19 22:48:57 -07:00
Eddie Hung a59f80834f SB_MAC16 ffCD to not pack same as ffO 2019-09-19 22:39:47 -07:00
Eddie Hung 8a94ce7aa5 Add an index 2019-09-19 20:04:44 -07:00
Eddie Hung 307b2dc8e5 Revert index to select 2019-09-19 14:46:53 -07:00
Eddie Hung 1a0f7ed09c Refactor ce{mux,pol} -> hold{mux,pol} 2019-09-19 14:27:25 -07:00
Eddie Hung 429c9852ce Add HOLD/RST support for SB_MAC16 2019-09-19 14:02:55 -07:00
Eddie Hung 2766465a2b Add support for SB_MAC16 CD and H registers 2019-09-19 12:14:33 -07:00
Eddie Hung c8310a6e76 Refactor ice40_dsp.pmg 2019-09-19 12:00:48 -07:00
Eddie Hung da8fe83f7a Tidy up ice40_dsp some more 2019-09-06 12:16:40 -07:00
Eddie Hung dc10559f31 Cleanup 2019-09-05 21:39:52 -07:00
Eddie Hung 5a2fc6fcb5 Refactor ice40_dsp 2019-09-05 18:06:59 -07:00
Eddie Hung 888ae1d05e Fix broken ice40_dsp 2019-09-05 17:58:19 -07:00
Eddie Hung 2983a35dc0 Update comment 2019-08-30 15:00:40 -07:00
Eddie Hung 4cc74346f1 Fix compile error 2019-08-20 20:27:05 -07:00
Eddie Hung b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Clifford Wolf eb80d3d43f Change pmgen default rule to reject, switch peepopt behavior to accept 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 22:47:59 +02:00
Eddie Hung 96ee7b9cf7 Simplify 2019-08-15 12:30:46 -07:00
Eddie Hung 27d5df9467 ffH -> ffFJKG 2019-08-15 12:19:34 -07:00
Eddie Hung aad97168b0 Fixes for reverting SigSpec helper functions 2019-08-14 10:22:33 -07:00
Eddie Hung 1b0e68db94 Revert changes to RTLIL::SigSpec methods 2019-08-13 17:09:28 -07:00
Eddie Hung 3dd3ab98c2 Improve ice40_dsp for non-fully-32-bit adders 2019-08-09 17:23:12 -07:00
Eddie Hung dfc878deb4 Another filter -> if 2019-08-09 16:23:32 -07:00
Eddie Hung e83f231927 Cleanup 2019-08-09 15:47:40 -07:00
Eddie Hung a002eba14a Fix check 2019-08-09 14:27:08 -07:00
Eddie Hung 82cbfada1b Revert "Fix typo" 
This reverts commit e3c39cc450.
 2019-08-09 14:14:28 -07:00
Eddie Hung 2c0be7aa5d Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing 2019-08-08 12:56:05 -07:00
Eddie Hung d90b8b081a Do not SigSpec::extract() beyond bounds 2019-08-07 13:58:26 -07:00
Eddie Hung cdf9c80134 Do not pack registers if (* keep *) 2019-08-07 12:57:10 -07:00
Eddie Hung c39b1a6fcf Add comment about supporting $dffe in ice40_dsp 2019-08-01 15:13:18 -07:00
Eddie Hung e19d33b003 Cope with sign extension in mul2dsp 2019-08-01 12:44:56 -07:00
Eddie Hung e3c39cc450 Fix typo 2019-08-01 10:00:01 -07:00
Eddie Hung a37574ccbf Fix muxAB logic 2019-07-23 14:52:14 -07:00
Eddie Hung dc0c853abe Simplify and fix for MACs 2019-07-23 14:20:34 -07:00
Eddie Hung 4f11ff8ebd Fix typo 2019-07-23 13:58:56 -07:00
Eddie Hung 068617f094 Pack hi and lo registers separately 2019-07-22 16:12:57 -07:00
Eddie Hung 4d71ab384d Rename according to vendor doc TN1295 2019-07-22 15:08:26 -07:00
Eddie Hung 304cefbbe2 Pack Y register 2019-07-22 15:05:16 -07:00
Eddie Hung 5a14b6e1f6 Pack adders not just accumulators 2019-07-22 13:01:49 -07:00
Eddie Hung e0720a8018 Restore old ffY behaviour 2019-07-19 22:47:08 -07:00
Eddie Hung f9d08a5e5e Cleanup 2019-07-19 20:25:28 -07:00
Eddie Hung 9ad11ea2cc Fine tune ice40_dsp.pmg, add support for packing subsets of registers 2019-07-19 10:57:32 -07:00
Eddie Hung 09411dd996 ice40_dsp to accept $__MUL16X16 too 2019-07-18 15:38:28 -07:00