Miodrag Milanovic
50e7221077
Add upto and offset to JSON ports
2019-06-21 19:47:25 +02:00
Miodrag Milanovic
3775763f51
Fix typo
2019-06-21 19:09:34 +02:00
Clifford Wolf
f15def325c
Added JSON upto and offset
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 15:22:17 +02:00
Clifford Wolf
78e7a6f6f2
Merge pull request #1119 from YosysHQ/eddie/fix1118
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Make genvar a signed type
2019-06-21 10:13:13 +02:00
Eddie Hung
9faeba7a66
Fix broken abc9.v test due to inout being 1'bx
2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
014606affe
Fix issue with part of PI being 1'bx
2019-06-20 17:38:16 -07:00
Eddie Hung
c27ab609fa
Make genvar a signed type
2019-06-20 16:04:12 -07:00
Eddie Hung
20119ee50e
Maintain "is_unsized" state of constants
2019-06-20 12:43:39 -07:00
Clifford Wolf
2428fb7dc2
Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays
2019-06-20 12:03:00 +02:00
Clifford Wolf
ec4565009a
Add "read_verilog -pwires" feature, closes #1106
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 14:38:50 +02:00
Tobias Wölfel
8b8af10f5e
Unpacked array declaration using size
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Allows fixed-sized array dimension specified by a single number.
This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560 .
But is split out of the original work.
2019-06-19 12:47:48 +02:00
Clifford Wolf
8d0cd529c9
Add defaultvalue attribute
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:37:11 +02:00
Clifford Wolf
6d64e242ba
Fix handling of "logic" variables with initial value
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:25:11 +02:00
Eddie Hung
fb90d8c18c
Cleanup
2019-06-16 09:34:26 -07:00
Eddie Hung
7876b5b8be
Cover __APPLE__ too for little to big endian
2019-06-14 12:40:51 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Eddie Hung
97d2656375
Resolve comments from @daveshah1
2019-06-14 12:00:02 -07:00
Eddie Hung
a3be25ab0d
Cleanup
2019-06-14 10:27:30 -07:00
Eddie Hung
d005568f2e
Add TODO to parse_xaiger
2019-06-14 10:11:13 -07:00
Eddie Hung
bc22e2e3ee
Optimise some more
2019-06-13 17:02:58 -07:00
Eddie Hung
d09d4e0706
Move ConstEvalAig to aigerparse.cc
2019-06-13 16:28:11 -07:00
Eddie Hung
d39a5a77a9
Add ConstEvalAig specialised for AIGs
2019-06-13 13:13:48 -07:00
Eddie Hung
342fc0a600
parse_xaiger to cope with inouts
2019-06-12 15:45:46 -07:00
Eddie Hung
b21d29598a
Consistency
2019-06-12 09:40:51 -07:00
Eddie Hung
f7a9769c14
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
Udi Finkelstein
4b56f6646d
Fixed brojen $error()/$info/$warning() on non-generate blocks
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(within always/initial blocks)
2019-06-11 02:52:06 +03:00
Eddie Hung
2b350401c4
Fix spacing from spaces to tabs
2019-06-07 15:44:57 -07:00
Eddie Hung
6934f4bdd5
Fix spacing (entire file is wrong anyway, will fix later)
2019-06-07 11:30:36 -07:00
Eddie Hung
d00ae1d6a8
Remove unnecessary std::getline() for ASCII
2019-06-07 11:28:25 -07:00
Eddie Hung
a04521c6b7
Fix read_aiger -- create zero driver, fix init width, parse 'b'
2019-06-07 11:07:15 -07:00
Clifford Wolf
211d85cfcc
Fixes and cleanups in AST_TECALL handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 12:41:09 +02:00
Clifford Wolf
a3bbc5365b
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
2019-06-07 12:08:42 +02:00
Clifford Wolf
a0b57f2a6f
Cleanup tux3-implicit_named_connection
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 11:46:16 +02:00
Clifford Wolf
b637b3109d
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection
2019-06-07 11:41:54 +02:00
tux3
88f5977093
SystemVerilog support for implicit named port connections
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This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
2019-06-06 18:07:49 +02:00
Clifford Wolf
b894187cf6
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn
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Added support for parsing attributes on port connections.
2019-06-06 12:34:05 +02:00
Maciej Kurc
03e0d3a17c
Fixed memory leak.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-05 10:42:43 +02:00
Clifford Wolf
36120fcc30
Only support Symbiotic EDA flavored Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-02 10:14:50 +02:00
Maciej Kurc
a6cadf6318
Added support for parsing attributes on port connections.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-31 14:58:43 +02:00
Clifford Wolf
2faa1d0e80
Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-30 10:04:26 +02:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor
2019-05-27 19:07:46 +02:00
Stefan Biereigel
cd12f2ddcf
remove leftovers from ast data structures
2019-05-27 18:01:44 +02:00
Stefan Biereigel
ed625a3102
move wand/wor resolution into hierarchy pass
2019-05-27 18:00:22 +02:00
Clifford Wolf
92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range
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Give error instead of asserting for invalid range, fixes #947
2019-05-27 13:26:12 +02:00
Miodrag Milanovic
84ffb21708
Give error instead of asserting for invalid range, fixes #947
2019-05-27 12:25:18 +02:00
Miodrag Milanovic
34417ce55f
Added support for unsized constants, fixes #1022
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Includes work from @sumit0190 and @AaronKel
2019-05-27 11:42:10 +02:00
Stefan Biereigel
85de9d26c1
fix assignment of non-wires
2019-05-23 17:55:56 +02:00
Stefan Biereigel
fd003e0e97
fix indentation across files
2019-05-23 13:57:27 +02:00
Stefan Biereigel
075a48d3fa
implementation for assignments working
2019-05-23 13:57:27 +02:00
Stefan Biereigel
9df04d7e75
make lexer/parser aware of wand/wor net types
2019-05-23 13:57:27 +02:00
Eddie Hung
7057753427
Rename label
2019-05-21 18:20:31 -07:00
Eddie Hung
b5a29460b9
Try again
2019-05-21 17:20:19 -07:00
Eddie Hung
1bff09f2ff
Fix warning
2019-05-21 16:26:20 -07:00
Kaj Tuomi
48ddbe52fb
Read bigger Verilog files.
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Hit parser limit with 3M gate design. This commit fix it.
2019-05-18 14:20:30 +03:00
Clifford Wolf
b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes
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Support for attributes on parameters and localparams for Verilog frontend
2019-05-16 14:21:18 +02:00
Maciej Kurc
ce4a0954bc
Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:44:16 +02:00
Henner Zeller
8eb2798776
Make the generated *.tab.hh include all the headers needed to define the union.
2019-05-14 21:07:26 -07:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
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Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf
1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
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Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf
7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
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Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00
Clifford Wolf
d187be39d6
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
2019-05-06 15:41:13 +02:00
Clifford Wolf
20268d12a5
Fix the other bison warning in ilang_parser.y
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 15:38:43 +02:00
Clifford Wolf
1cd1b5fc1a
Add "real" keyword to ilang format
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:00:40 +02:00
Clifford Wolf
c7f2e93024
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
2019-05-06 11:46:10 +02:00
Ben Widawsky
a98069d762
verilog_parser: Fix Bison warning
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As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
%name-prefix "frontend_verilog_yy"
For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html
Compile tested only.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-05-05 19:36:27 -07:00
Clifford Wolf
70d0f389ad
Merge pull request #988 from YosysHQ/clifford/fix987
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Add approximate support for SV "var" keyword
2019-05-04 21:58:25 +02:00
Clifford Wolf
66d6ca2de2
Add support for SVA "final" keyword
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 09:25:32 +02:00
Clifford Wolf
87426f5a06
Improve write_verilog specify support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:46:24 +02:00
Clifford Wolf
9804c86e87
Add approximate support for SV "var" keyword, fixes #987
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 07:52:51 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Eddie Hung
c7d7d8ad1b
For hier_tree::Elaborate() also include SV root modules (bind)
2019-05-03 20:53:25 +02:00
Eddie Hung
3ea54ec400
Fix verific_parameters construction, use attribute to mark top netlists
2019-05-03 20:53:25 +02:00
Eddie Hung
a27b42e975
WIP -chparam support for hierarchy when verific
2019-05-03 20:53:25 +02:00
Eddie Hung
0f1a4cc03c
verific_import() changes to avoid ElaborateAll()
2019-05-03 20:53:25 +02:00
Udi Finkelstein
ac10e7d96d
Initial implementation of elaboration system tasks
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(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Clifford Wolf
6bbe2fdbf3
Add splitcmplxassign test case and silence splitcmplxassign warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
Clifford Wolf
3b6a02d3a7
Fix width detection of memory access with bit slice, fixes #974
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:57:26 +02:00
Clifford Wolf
59d74a3348
Re-enable "final loop assignment" feature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:02:39 +02:00
Clifford Wolf
e35fe1344d
Disabled "final loop assignment" feature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 20:22:50 +02:00
Clifford Wolf
9c7d23446d
Merge pull request #972 from YosysHQ/clifford/fix968
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Add final loop variable assignment when unrolling for-loops
2019-04-30 18:09:44 +02:00
Clifford Wolf
84f3a796e1
Include filename in "Executing Verilog-2005 frontend" message, fixes #959
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:37:46 +02:00
Clifford Wolf
9af825e31e
Add final loop variable assignment when unrolling for-loops, fixes #968
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
Clifford Wolf
64925b4e8f
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
Eddie Hung
d9c915042a
Move clean from aigerparse to abc9
2019-04-23 13:42:35 -07:00
Clifford Wolf
4575e4ad86
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
012c6af088
Allow $specify[23] cells in blackbox modules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
b232e027bf
Checking and fixing specify cells in genRTLIL
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
41b843c27b
Un-break default specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
3cc95fb4be
Add specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Eddie Hung
5f30a8795d
Tidy up
2019-04-22 17:47:05 -07:00
Eddie Hung
8f30019b68
Revert "Temporarily remove 'r' extension"
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This reverts commit eaf3c24772
.
2019-04-22 17:41:21 -07:00
Eddie Hung
eaf3c24772
Temporarily remove 'r' extension
2019-04-22 11:54:19 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
bc98a463a4
Merge pull request #952 from YosysHQ/clifford/fix370
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Determine correct signedness and expression width in for-loop unrolling
2019-04-22 20:10:46 +02:00
Clifford Wolf
4ad0ea5c3c
Determine correct signedness and expression width in for loop unrolling, fixes #370
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
Clifford Wolf
e158ea2097
Add log_debug() framework
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 17:25:52 +02:00
Clifford Wolf
b40af877f3
Merge pull request #909 from zachjs/master
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support repeat loops with constant repeat counts outside of constant functions
2019-04-22 08:51:34 +02:00