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1391 Commits

Author SHA1 Message Date
whitequark f6412d7109 select: print selection if a -assert-* flag causes an error. 2018-12-16 15:44:29 +00:00
Clifford Wolf 0d9c850a07
Merge pull request #735 from daveshah1/trifixes 
deminout fixes
 2018-12-16 16:02:21 +01:00
Clifford Wolf f53e19cc71 Fix equiv_opt indenting 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-16 15:57:28 +01:00
Clifford Wolf 2a681909df
Merge pull request #724 from whitequark/equiv_opt 
equiv_opt: new command, for verifying optimization passes
 2018-12-16 15:54:26 +01:00
Clifford Wolf a2154c1be0
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata 
memory_bram: Fix initdata bit order after shuffling
 2018-12-16 15:53:44 +01:00
Clifford Wolf a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming 
Proof-of-concept: preserve naming through ABC using dress
 2018-12-16 15:41:30 +01:00
Clifford Wolf 19ca4e2ac3
Merge pull request #722 from whitequark/rename_src 
rename: add -src, for inferring names from source locations
 2018-12-16 15:28:29 +01:00
Clifford Wolf 556341a77f
Merge pull request #720 from whitequark/master 
lut2mux: handle 1-bit INIT constant in $lut cells
 2018-12-16 15:27:23 +01:00
David Shah 4c59447168 deminout: Consider $tribuf cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-12 17:17:40 +00:00
David Shah d3fe9465f3 deminout: Don't demote constant-driven inouts to inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-12 16:50:46 +00:00
Graham Edgecombe 4fef9689ab memory_bram: Fix initdata bit order after shuffling 
In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.

This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).

This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
 2018-12-11 21:02:49 +00:00
whitequark 7ff5a9db2d equiv_opt: pass -D EQUIV when techmapping. 
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
 2018-12-07 17:20:34 +00:00
whitequark c38ea9ae65 equiv_opt: new command, for verifying optimization passes. 2018-12-07 17:20:34 +00:00
whitequark 7ec740b7ad opt_lut: leave intact LUTs with cascade feeding module outputs. 2018-12-07 17:13:52 +00:00
whitequark 9eb03d458d opt_lut: show original truth table for both cells. 2018-12-07 17:04:41 +00:00
whitequark a8ab722824 opt_lut: add -limit option, for debugging misoptimizations. 2018-12-07 16:36:26 +00:00
David Shah 1dfb2fecab abc: Preserve naming through ABC using 'dress' command 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 15:05:07 +00:00
Clifford Wolf 643f858acf Bugfix in opt_expr handling of a<0 and a>=0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:29:21 +01:00
whitequark a9baee4b24 rename: add -src, for inferring names from source locations. 2018-12-05 20:35:13 +00:00
whitequark d1f2cb01dc lut2mux: handle 1-bit INIT constant in $lut cells. 
This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
 2018-12-05 19:27:48 +00:00
whitequark 88217d0157 opt_lut: simplify type conversion. NFC. 2018-12-05 19:12:02 +00:00
Clifford Wolf 2d98db73e3 Rename opt_lut.cpp to opt_lut.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-05 18:03:58 +01:00
whitequark 45cb6200af opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. 2018-12-05 16:30:37 +00:00
whitequark e603484070 opt_lut: always prefer to eliminate 1-LUTs. 
These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
 2018-12-05 16:30:37 +00:00
whitequark 59eea0183f opt_lut: collect and display statistics. 2018-12-05 16:30:37 +00:00
whitequark e54c7e951c opt_lut: refactor to use a worker. NFC. 2018-12-05 16:30:37 +00:00
whitequark 9e072ec21f opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-05 16:30:37 +00:00
Clifford Wolf c800e3bb16 Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-04 23:30:23 +01:00
Clifford Wolf 70c417174d
Merge pull request #702 from smunaut/min_ce_use 
Add option to only use DFFE is the resulting E signal would be use > N times
 2018-12-04 14:29:21 -08:00
Clifford Wolf 47c89d600c
Merge pull request #676 from rafaeltp/master 
Splits SigSpec into bits before calling check_signal_in_fanout (solves #675)
 2018-12-01 04:11:19 +01:00
Sylvain Munaut 8d3ab626ea dff2dffe: Add option for unmap to only remove DFFE with low CE signal use 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-27 21:50:42 +01:00
Clifford Wolf ab97eddee9 Add iteration limit to "opt_muxtree" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-20 17:56:47 +01:00
Niels Moseley cfc9b9147c DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info. 2018-11-06 12:11:52 +01:00
Clifford Wolf 719e29404a Allow square brackets in liberty identifiers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-05 12:33:33 +01:00
Niels Moseley 04cd179696 Liberty file newline handling is more relaxed. More descriptive error message 2018-11-03 18:38:49 +01:00
Niels Moseley d1e8249f9a Report an error when a liberty file contains pin references that reference non-existing pins 2018-11-03 18:07:51 +01:00
rafaeltp f8b97e21f3 using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal 2018-10-21 11:32:44 -07:00
rafaeltp 7b964bfb83 cleaning up for PR 2018-10-20 18:02:59 -07:00
rafaeltp ce069830c5 fixing code style 2018-10-20 17:57:26 -07:00
rafaeltp 0ad4321781 solves #675 2018-10-20 17:50:21 -07:00
Ruben Undheim 436e3c0a7c Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
Ruben Undheim 397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Clifford Wolf 6514443a5c
Merge pull request #672 from daveshah1/fix_bram 
memory_bram: Reset make_outreg when growing read ports
 2018-10-19 16:09:11 +02:00
David Shah 3420ae5ca5 memory_bram: Reset make_outreg when growing read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 14:46:31 +01:00
Clifford Wolf f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces 
Support for SystemVerilog interfaces and modports
 2018-10-18 10:58:47 +02:00
Ruben Undheim c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
tklam f4343b3dc7 stop check_signal_in_fanout from traversing FFs 2018-10-13 23:24:24 +08:00
tklam 302edf0429 stop check_signal_in_fanout from traversing FFs 2018-10-13 23:11:19 +08:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
tklam b86eb3deef fix bug: pass by reference 2018-09-26 17:57:39 +08:00
TK Lam 2b89074240 Fix issue #639 2018-09-26 16:11:45 +08:00
Clifford Wolf 592a82c0ad
Merge pull request #625 from aman-goel/master 
Minor revision to -expose in setundef pass
 2018-09-14 12:36:13 +02:00
acw1251 5fe16c25b8 Fixed minor typo in "sim" help message 2018-09-12 18:34:27 -04:00
Aman Goel 75c1f8d241 Minor revision to -expose in setundef pass 
Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
 2018-09-10 21:44:36 -04:00
Clifford Wolf 05466790a6
Merge pull request #606 from cr1901/show-win 
`show` pass `-format` and `-viewer` improvements on Windows
 2018-08-19 15:25:46 +02:00
Aman Goel 83b41260f6 Revision to expose option in setundef pass 
Corrects indentation

Simplifications and corrections
 2018-08-18 09:08:07 +05:30
Aman Goel 61f002c908
Merge pull request #3 from YosysHQ/master 
Updates from official repo
 2018-08-18 08:18:40 +05:30
William D. Jones 7ce7ea2eb4 Update show pass documentation with Windows caveats. 2018-08-15 17:18:19 -04:00
William D. Jones 9f91c62348 Fix run_command() when using -format and -viewer in show pass. 2018-08-15 17:18:19 -04:00
Clifford Wolf 67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf 0eaab6cd1d Add missing <deque> include (MSVC build fix) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 15:21:59 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf 87aef8f0cc Add async2sync pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-19 15:31:12 +02:00
Aman Goel 5dcb899e76
Merge pull request #2 from YosysHQ/master 
Merging with official repo
 2018-07-18 11:34:18 -04:00
David Shah 459d367913 ecp5: Adding synchronous set/reset support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-14 16:18:01 +02:00
Aman Goel 4d343fc1cd Merging with official repo 2018-07-04 15:14:28 -04:00
Clifford Wolf 5f2bc1ce76 Add automatic verific import in hierarchy command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 23:45:01 +02:00
Clifford Wolf 675a44b41a Be slightly less aggressive in "deminout" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-19 14:29:38 +02:00
Edmond Cote d89560a0ba
Include module name for area summary stats 
The PR prints the name of the module when displaying the final area count.

Pros:
- Easier for the user to `grep` for area information about a specific module

Cons:
- Arguably more verbose, less "pretty" than author desires

Verification:
~~~~
30c30
<    Chip area for this module: 20616.349000
---
>    Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
<    Chip area for this module: 88.697700
---
>    Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
<    Chip area for this module: 20705.046700
---
>    Chip area for top module '\picorv32_axi': 20705.046700
~~~~
 2018-06-18 17:29:01 -07:00
Clifford Wolf f273291dfe Add setundef -anyseq / -anyconst support to -undriven mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 11:57:28 +02:00
Clifford Wolf 4cd6d5556a Add "setundef -anyconst" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 11:49:58 +02:00
Clifford Wolf 3ab79a231b Bugfix in handling of array instances with empty ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-31 18:09:31 +02:00
Clifford Wolf cee4b1e6bc Disable memory_dff for initialized FFs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 17:16:15 +02:00
Clifford Wolf 74efafc1cf Add some cleanup code to memory_nordff 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 16:42:06 +02:00
Robert Ou 9763e4d830 Fix infinite loop in abc command under emscripten 2018-05-18 22:42:39 -07:00
Robert Ou bfce3a7479 Add an option to statically link abc into yosys 
This is currently incomplete because the output filter no longer works.
 2018-05-18 22:35:28 -07:00
Aman Goel 6e63df6dd0 Correction to -expose with setundef 2018-05-15 13:06:23 -04:00
Clifford Wolf fe80b39f56 Fix iopadmap for loops between tristate IO buffers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 14:02:27 +02:00
Clifford Wolf edd297fb1c Fix iopadmap for cases where IO pins already have buffers on them 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 13:13:43 +02:00
Aman Goel 8b9a8c7f91 Minor correction 
Minor typo error correction in -expose with setundef
 2018-05-14 18:58:49 -04:00
Aman Goel b4a303a1b7 Corrections to option -expose in setundef pass 2018-05-13 20:13:54 -04:00
Aman Goel 9286acb687 Add option -expose to setundef pass 
Option -expose converts undriven wires to inputs.

Example usage: setundef -undriven -expose [selection]
 2018-05-13 16:53:35 -04:00
Clifford Wolf 0fad1570b5 Some cleanups in setundef.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-13 16:36:12 +02:00
Christian Krämer c1ecb1b2f1 Add "#ifdef __FreeBSD__" 
(Re-commit e3575a8 with corrected author field)
 2018-05-13 13:08:26 +02:00
Clifford Wolf 1167538d26 Revert "Add "#ifdef __FreeBSD__"" 
This reverts commit e3575a86c5.
 2018-05-13 13:06:36 +02:00
Clifford Wolf 587056447e Add optimization of tristate buffer with constant control input 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 15:18:27 +02:00
Clifford Wolf 11406a8082 Add "hierarchy -simcheck" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 13:59:13 +02:00
Johnny Sorocil e3575a86c5 Add "#ifdef __FreeBSD__" 2018-05-05 13:02:44 +02:00
Clifford Wolf 145c685de0 Add ABC FAQ to "help abc" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-04 21:59:31 +02:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Clifford Wolf 705c366a91 Added missing dont_use handling for SR FFs to dfflibmap 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-05 11:01:45 +02:00
Clifford Wolf 665eec3d53 Removed $timescale from "sat" command VCD writer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-29 12:38:41 +02:00
Clifford Wolf ee3c12d6d9 Chenged "extensions_map" to "extensions_list" in hierarchy.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 14:12:57 +02:00
Sergi Granell f93f8aaa11 passes/hierarchy: Reduce code duplication in expand_module 
This also makes it easier to add new file extensions support.

Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
 2018-03-27 09:35:20 +02:00
Clifford Wolf 491c352da7 Add .sv support to "hierarchy -libdir" 2018-03-26 21:19:00 +02:00
Clifford Wolf 08225f49a4 Add "expose -input" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-12 13:52:52 +01:00
Clifford Wolf 83ffb23739 Add "setundef -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-12 13:52:35 +01:00
Clifford Wolf a74f805ba0 Fix handling of src attributes in flatten 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 13:55:30 +01:00
Clifford Wolf 73c01dca65 Add "memory_nordff" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 23:31:51 +01:00