8b1c5df909
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 15:23:01 +02:00
05278ec738
[DATA] Update HK views (timing clean)
2021-11-25 12:54:22 +02:00
fe21089505
Updated caravan with the same addition of four spare logic blocks
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as was made to caravel.
2021-11-24 17:10:05 -05:00
be98da0fe6
Added spare logic block to caravel layout and verilog GL, wired
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it to the power supply, and checked top-level LVS.
2021-11-24 16:50:22 -05:00
83e150bf25
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00
9b1a18a15e
Finished drawing all of the analog connections to meet cleanly at
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the user analog project boundary.
2021-11-23 17:32:52 -05:00
0114df40ae
Added additional power routing from the sides of Caravel to the
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user project power ring. If that is incompatible with user
projects and/or the XOR check, then this commit might need to be
reverted.
2021-11-23 16:49:23 -05:00
0ba8884b00
Added a motto for each chip. Just because.
2021-11-23 15:19:41 -05:00
1ff48245e8
Pushing final layout of Caravan, now LVS clean.
2021-11-23 14:06:14 -05:00
5d3f2a26f4
Corrected the Caravel layout and the Caravel and Caravan GL netlists
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to resolve the problem with the typo that caused the propagated
GPIO serial load, reset, and clock signals to get scrambled on the
user2 side. Caravel is now LVS clean again (Caravan needs layout
work).
2021-11-23 11:47:17 -05:00
08a2c90940
Made updates to correct LVS errors in caravan. Found one major error in the RTL
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verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to
correct this; still need to correct the layouts. The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing. Will route this by hand.
2021-11-22 22:35:52 -05:00
e86831b188
Final edits to make caravel LVS clean.
2021-11-22 16:51:35 -05:00
aeffe4756a
[DATA] Add caravan layout
2021-11-22 23:10:25 +02:00
38f64d08a3
[DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views
2021-11-22 23:08:25 +02:00
cd68a2aeff
Made several corrections to errors found in the netlists: (1)
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Fixed rstb_h, which was being input to low-voltage blocks. (2)
Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not
output from housekeeping as they should be; the solution was
to tie the INP_DIS lines low at the pad by connecting them to
the TIE_LO_ESD line. This should probably be addressed in
housekeeping but would change the current pinout.
2021-11-22 15:21:06 -05:00
515b5a54f2
Updates for LVS. Only LVS issue remaining for caravel is how to get the
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ground domains to extract independently.
2021-11-22 12:00:55 -05:00
1eb023d973
Added isolated substrate markers in mgmt_protect_hv, should fix the
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last of the LVS issues.
2021-11-21 23:04:45 -05:00
6eb8bb54de
Several more LVS corrections, including fixing a label in chip_io that
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got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared. The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
2021-11-21 22:58:39 -05:00
5262f35610
Modifications done as part of LVS on the caravel top level.
2021-11-21 22:07:16 -05:00
60bdc7e6a4
Moved some supply lines over in chip_io_alt for Caravan to make it
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more compatible with the routing that was copied over from Caravel.
2021-11-21 13:00:44 -05:00
d87d60cb9b
Finished first draft of the caravel power routing (prior to LVS).
2021-11-21 12:41:46 -05:00
29dbc77591
More power routing, still a work in progress.
2021-11-20 22:53:18 -05:00
6570429234
Continued work on the power routing. Also updated the management
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core wrapper view with the LEF view from caravel_pico.
2021-11-20 22:04:46 -05:00
8f75362f82
Start of power routing.
2021-11-20 18:04:43 -05:00
b0d3217280
Replaced the gpio_defaults_block_0000.mag layout with gpio_defaults_block.mag
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so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block). Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there. Reinstated the copyright, user ID text, open source
logo, and Caravel logo. Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
2021-11-20 13:43:49 -05:00
331fdee2bb
[DATA] Update HK module (li1 routing: 249um)
2021-11-20 15:13:16 +02:00
5cd3843f00
[DATA] Update gpio_control_block (li1 used 2um)
2021-11-20 14:43:20 +02:00
37fb2d6766
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 13:07:23 +02:00
ededa9ed35
[DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core
2021-11-19 16:51:28 +02:00
866755f228
[DATA] Update mgmt_protect mag/gds to remove the shorted power nets
2021-11-19 15:50:36 +02:00
bf6ad67934
[DATA] Update gpio_control_block pin order to fix shorts at the top level
2021-11-19 13:13:24 +02:00
581a22de6a
[DATA] Update mgmt_protect (removed all li1 routing )
2021-11-19 13:11:18 +02:00
2574eada93
[DATA] Add initial caravel layout
2021-11-19 01:37:10 +02:00
61bf3c651e
[DATA] Update mgmt_protect pin placement
2021-11-19 01:33:11 +02:00
53b3a9013e
[DATA] Update HK pin placement
2021-11-19 01:30:14 +02:00
37a07e291b
[DATA] Update digital_pll pin placement to have it align with the HK
2021-11-19 01:28:40 +02:00
64bdd6230d
[DATA] Update caravel_clocking module floorplan
2021-11-19 01:26:29 +02:00
1b300d7b59
[DATA] Add digital user project wrapper
2021-11-17 13:13:11 +02:00
559675d392
Corrected chip_io and chip_io_alt layouts to restore the accidentally
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deleted "resetb_core_h" port label. Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
2021-11-15 17:13:43 -05:00
f28950695d
Made adjustments to the padframe routing to move all routes closer
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to the padframe and free up more space for routing in the chip
interior.
2021-11-15 11:52:08 -05:00
aefa72281c
Added the files for the simple_por block design, and placed the latest
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hardened macro components into the caravel and caravan layouts.
2021-11-15 10:34:52 -05:00
72b2c724c9
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 15:50:43 +02:00
4c9f7630ff
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
2021-11-15 13:24:42 +02:00
56f672bbd8
[DATA] Add HK views
2021-11-15 13:23:54 +02:00
85a1ffc5aa
[DATA] Add views for the mgmt_protect
2021-11-15 13:21:52 +02:00
67e48e53c5
Corrected minor DRC errors around the padframe cell and in the new
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caravan logo layout. Current design is DRC clean with the new
open_pdks maglef views of the I/O cells.
2021-11-12 16:12:12 -05:00
46dd9493f6
Removed some vestiges of top-level routing that were left over
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from the previous version of the caravel and caravan layouts.
2021-11-12 13:45:58 -05:00
d5ef31e391
Added an empty management core wrapper to the caravel top level.
2021-11-12 12:17:52 -05:00
27fdba364b
Added user 1.8V power supply rails to the chip_io and chip_io_alt
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layouts. Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell. These
internal lines were previously in the power routing cells.
2021-11-10 17:13:43 -05:00
38dbd8d5d9
Added logo graphic for Caravan.
2021-11-09 22:47:31 -05:00
8da7d5124b
Added a logo for Caravel.
2021-11-09 17:18:20 -05:00
89bb33fbc0
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
2021-11-08 13:35:16 +02:00
bee7b4ed78
Add initial config for the digital_pll
2021-11-08 13:34:59 +02:00
27e0c94997
Added caravan top level and seeded with the GPIO control blocks,
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default blocks, and updated copyright.
2021-11-06 22:34:49 -04:00
cd906cbf8a
Updated the copyright block for the new designs. Added caravel
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layout and placed the GPIO control blocks and default blocks.
2021-11-06 22:13:19 -04:00
6a93ea582d
Added a script which parses the file "user_defines.v" in
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verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file. Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
2021-11-06 21:19:42 -04:00
f53590d4b5
Split the layout of the GPIO defaults block into three versions, for the
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three parameterized values used in the RTL verilog. Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
2021-11-06 13:28:26 -04:00
33140b67a5
Edited the gpio_defaults_block layout like the user_id_programming
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cell to have landing sites for vias on both the HI and LO pins of
each conb_1 cell, in preparation for via programming.
2021-11-06 12:59:49 -04:00
59076d499a
Update gpio_defaults_block to align the pins with the gpio_control_block
2021-11-05 23:27:32 +02:00
49c506f052
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 18:36:43 +02:00
e68664101c
Update gpio_control_block
2021-11-05 16:54:55 +02:00
53b09f43d1
Add gpio_defaults_block views
2021-11-05 12:33:36 +02:00
78ce7265c1
Update gpio_control block
2021-11-04 17:58:58 +02:00
cb9990f97e
harden gpio_control_block
2021-11-04 16:19:12 +02:00
ba932643e6
Changed the chip_io and chip_io_alt layouts to implement the
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continuous ring of vccd and vssd. The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
2021-11-03 15:57:46 -04:00
9fb3925649
Updated the OSHW (open source hardware) icon graphic layout, which was
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badly digitized, and not taking advantage of the allowance of 45 degree
angles on metal5.
2021-11-01 17:25:34 -04:00
dd66d1e5ca
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 21:43:09 -04:00
3a57940371
Revised the management protect block to include protections against
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an unconnected wishbone bus (unconnected inputs). Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
2021-10-27 19:36:43 -04:00
a7148378a0
Added as many of the magic database layout files as are expected to remain
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unchanged between the caravel and caravel_openframe repositories.
2021-10-26 10:27:03 -04:00
manarabdelaty
Tim Edwards