gpio_signal_buffering_alt cell (caravan chip). This was
previously done for gpio_signal_buffering (caravel chip) but
the same thing had not previously been done for caravan.
* Corrected missing part of porb_h route in the caravan chip_io_alt
layout. Correcting the indexing of the "mprj_io_one" connections
to "mgmt_io_oeb" on the left-hand side of caravan, as they were
connecting back to the right side and making a mess of wiring,
instead of being wired locally directly to the nearest I/O.
* Apply automatic changes to Manifest and README.rst
* Corrected the unconnected mgmt_io_in inputs to housekeeping on
the caravan chip (which correspond to the GPIOs that do not exist
in caravan) by connecting them to the "zero" outputs of the
closest GPIO control blocks.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* update caravel with tying `porb_h_in` with `por_l_in` at the `mgmt_core_wrapper` in the top-level layout:
- `porb_h_in` shouldn't be left floating as it is an input to `clkbuf_16`
* add caravel-eco.gds (same as caravel.gds)
* Syntax changes that are non-functional from a synthesis perspective.
There are a few errors that are caught by commercial tools and halt
synthesis, which are handled more gracefully by the open source
tool flow. In housekeeping.v: Some wires declared after they are
used. In housekeeping_spi.v: A non-blocking "=" assignment used
where a blocking "<-" assignment was intended.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* cocotb - updates related to enable simulating caraval using iverilog
* Apply automatic changes to Manifest and README.rst
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
* Fixed caravan top level power routing and updated views for mag, gds and lef
* caravan(rtl): updates
~ typos fix
- remove unused pin in chip_io_alt
+ add caravan_power_routing verilog
* Apply automatic changes to Manifest and README.rst
* ~ update caravan openlane configs to add extra cell references
~ correct placment and cell names of some macro in caravan interactive script
* reharden: caravan
+ add non functional blocks
+ add an initial iteration of caravan
* Apply automatic changes to Manifest and README.rst
* Revert "Fixed caravan top level power routing and updated views for mag, gds and lef"
This reverts commit 70628f748a.
* fixed caravan top level power routing
* reharden: caravan
based on new power routing
~ guard rtl chip_io power pins in the power macro guard
* Apply automatic changes to Manifest and README.rst
* fixed caravan top level power routing
* rehadren: caravan
+ add caravan signal routing to openlane run
~ change rtl to guard power and analog against routing by
openlane by ifndef TOP_ROUTING
~ add pr bounadry for caravan signal routing to fix origin issues
* Apply automatic changes to Manifest and README.rst
* fix power connection in buffering block and regenerate gl
* Apply automatic changes to Manifest and README.rst
* updated views for caravan
* Added extract unique to lvs-gds-cell target. (#313)
* This fixes errors in the top level RTL of caravan that failed to
hook up the buffers through the SoC correctly.
* Apply automatic changes to Manifest and README.rst
* reharden: caravan
~ rtl updated
* fixed caravan mag top level
* updated views for caravan + signoff
* fixed top level cell name
* fix syntax error related to signal initialization place in caravan (#319)
* fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit
* Apply automatic changes to Manifest and README.rst
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
* Apply automatic changes to Manifest and README.rst
Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com>
Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
* added views for each step of generating final caravel.gds
* generated the right caravel and caravel-eco gds
* renamed caravel_signoff and removed caravel-non-eco
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
* reharden: caravel
~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing
* update pdn for `caravel_clocking` & `digital_pll`
* added script to update and generate the power routing views
* ~ run update_power_routing_views from the caravel root with prboundary
* fix output message
* added power routing lef, mag and gds
* fix update_power_routing_views saving wrong cell name
* reharden: caravel
~ incorperate pdn changes
~ re-extract spefs
* fix caravel_power_routing views
* fix abs path in maglef views
* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect
* generate a new chip_io gds
* regenerate gpio_control_block due to mag and gds not in sync
* reharden: caravel
~ change config to pass clean routing
~ use updated views of macros
* lvs clean views
* add caravel top-level generated sdf for all corners
* fix absolute path for mgmt_core_wrapper
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>
~ increase width for more spread decaps
+ add or cells to cell exclude
~ change placement density in accordance to area
~ change padding to allow for space for decaps
~ increase height for more spread decap insertion
+ add or cells to cell exclude
~ adjust pdn to have an offset half to pitch
~ change placement density in accordance to area
~ change padding to allow for space for decap insertion
~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys
!need to verify that the oscillator remains untouched
the RTL, but cleaned up for macro definitions; this can be used
for LVS. The decap cells were hand-edited in because there is
no way to devine them from the RTL source.
being buffered pass through the buffer macros. Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
same file), errors (buffer output pin name, power supplies not
passed at the top level). Corrected a major error that prevented
the use of the buffers in simulation, so this was not previously
verified by simulation. The buffering has now been properly
verified.
R. Timothy Edwards
M0stafaRady
marwaneltoukhy
kareem
Marwan Abbas
passant5
M0stafaRady
Jeff DiCorpo
mo-hosni
Mohamed Shalan
Passant