mirror of https://github.com/efabless/caravel.git
fix bug in bitbang_no_cpu_all_o testbench
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@ -80,6 +80,7 @@ async def bitbang_no_cpu_all_o(dut):
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await clock_in_right_o_left_i_standard(cpu,0) # 1 and 36
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await clock_in_end_output(cpu) # 0 and 37 and load
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await caravelEnv.release_csb()
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
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@ -338,7 +338,7 @@ class RunRegression:
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def update_reg_log(self):
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file_name=f"sim/{os.getenv('RUNTAG')}/runs.log"
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f = open(file_name, "w")
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f.write(f"{'Test':<25} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
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f.write(f"{'Test':<33} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
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for test,sim_types in self.tests.items():
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for sim_type,corners in sim_types.items():
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for corner,status in corners.items():
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