diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py
index e80edb9d..222d2ee8 100644
--- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py
+++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py
@@ -80,6 +80,7 @@ async def bitbang_no_cpu_all_o(dut):
     await clock_in_right_o_left_i_standard(cpu,0) # 1	and 36	
     await clock_in_end_output(cpu)		          # 0   and 37 and load
 
+    await caravelEnv.release_csb()
     await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0) 
     await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) 
 
diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py
index 01b36271..9c37c660 100755
--- a/verilog/dv/cocotb/verify_cocotb.py
+++ b/verilog/dv/cocotb/verify_cocotb.py
@@ -338,7 +338,7 @@ class RunRegression:
     def update_reg_log(self):
         file_name=f"sim/{os.getenv('RUNTAG')}/runs.log"
         f = open(file_name, "w")
-        f.write(f"{'Test':<25} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
+        f.write(f"{'Test':<33} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
         for test,sim_types in self.tests.items():
             for sim_type,corners in sim_types.items():
                 for corner,status in corners.items():