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caravel
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86 Commits

Author SHA1 Message Date
Kareem Farid c84e1393e7
updates to top level caravel (#59) 
* REVERT ME: temporarily match simple_por pin in verilog with lef

* - update configs
- add patch file for power routing def

* - update the following caravel toplevel views
    - gl
    - mag
    - def
- add caravel power routing def

* Apply automatic changes to Manifest and README.rst

* update gl mag and def for caravel

* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"

This reverts commit b70c27c69f.

* update caravel gds

* Apply automatic changes to Manifest and README.rst

* Added text and logo cells back into the caravel top level.  Put an
isolated ground marker layer on the xres_buf layout.  Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v.  Updated the copyright block text.
Corrected DRC errors in the top level routing.

Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
 2022-04-08 09:31:33 -07:00
Kareem Farid dcebeed7e7
Mgmt protect update (#58) 
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect

* mgmt_protect updated

* mgmt_protect updated

* remove some via3 to fix power shorts

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
 2022-04-08 09:29:49 -07:00
Kareem Farid e3b9a99154
- update gpio_control_block config (#57) 
- update gpio_control_block views
- gitignore gds/*gds
 2022-04-08 09:27:51 -07:00
manarabdelaty 981043cb7b [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
manarabdelaty e60957d73b [DATA] Update sdf for chip_io to include pad delays 2021-12-16 15:58:58 +02:00
manarabdelaty bd88221d17 [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
manarabdelaty 966b1f22bb [DATA] Update digital_pll 2021-12-07 13:19:02 +02:00
manarabdelaty 3fa797bbf8 [DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks 2021-12-05 19:48:02 +02:00
manarabdelaty aa766f9144 [DATA] Update caravel_clocking module 2021-12-05 19:44:28 +02:00
manarabdelaty ef1019b62a [DATA] Update caravel_clocking 2021-12-02 22:50:20 +02:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
manarabdelaty c4efcec989 [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
manarabdelaty 8b1c5df909 [DATA] Update caravel_clocking module (timing clean) 2021-11-25 15:23:01 +02:00
manarabdelaty 05278ec738 [DATA] Update HK views (timing clean) 2021-11-25 12:54:22 +02:00
manarabdelaty 83e150bf25 [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
manarabdelaty aeffe4756a [DATA] Add caravan layout 2021-11-22 23:10:25 +02:00
manarabdelaty 38f64d08a3 [DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views 2021-11-22 23:08:25 +02:00
manarabdelaty 1c18c1dae9 [DATA] Update caravel 2021-11-20 17:28:59 +02:00
manarabdelaty 331fdee2bb [DATA] Update HK module (li1 routing: 249um) 2021-11-20 15:13:16 +02:00
manarabdelaty 37fb2d6766 [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) 2021-11-20 13:07:23 +02:00
manarabdelaty ededa9ed35 [DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core 2021-11-19 16:51:28 +02:00
manarabdelaty 581a22de6a [DATA] Update mgmt_protect (removed all li1 routing ) 2021-11-19 13:11:18 +02:00
manarabdelaty 2574eada93 [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
manarabdelaty 61bf3c651e [DATA] Update mgmt_protect pin placement 2021-11-19 01:33:11 +02:00
manarabdelaty 53b3a9013e [DATA] Update HK pin placement 2021-11-19 01:30:14 +02:00
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
manarabdelaty 64bdd6230d [DATA] Update caravel_clocking module floorplan 2021-11-19 01:26:29 +02:00
manarabdelaty 1b300d7b59 [DATA] Add digital user project wrapper 2021-11-17 13:13:11 +02:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00
manarabdelaty 85a1ffc5aa [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
manarabdelaty 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
manarabdelaty 53b09f43d1 Add gpio_defaults_block views 2021-11-05 12:33:36 +02:00
manarabdelaty 78ce7265c1 Update gpio_control block 2021-11-04 17:58:58 +02:00
manarabdelaty cb9990f97e harden gpio_control_block 2021-11-04 16:19:12 +02:00