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737 Commits

Author SHA1 Message Date
tangxifan 61ab543e2a [Doc] Update sphinx bibtex version requirement to avoid imcompatible versions 2020-12-14 10:57:59 -07:00
Ganesh Gore 13fc082cb3 [SOFA_HD] Updated verification script 2020-12-14 01:16:30 -07:00
Ganesh Gore 5c12369380 [SOFA_HD] Updated netlist + Caravel precheck passed 2020-12-14 01:16:00 -07:00
Ganesh Gore 967905e046 [SOFA_HD] Updated netlist and task 2020-12-14 01:14:14 -07:00
Ganesh Gore fa87753d62 [Cleanup] Renamed projects to SOFA-HD and QLSOFA-HD 2020-12-14 00:45:11 -07:00
Ganesh Gore 9f9897c5e2 [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00
Ganesh Gore 0672f01e3a [Cleanup] Removed unused SDCs 2020-12-14 00:31:03 -07:00
tangxifan 8def618a52
Merge pull request #66 from lnis-uofu/xt_dev 
FPGA I/O cell Update
 2020-12-11 18:08:18 -07:00
tangxifan b38a948a56 [Doc] Add testing waveform example to documentation 2020-12-11 17:24:28 -07:00
tangxifan 63bc60ccdd [Git] Relax the LFS application to get rid of small files 2020-12-11 16:25:23 -07:00
tangxifan 1e490c1714 [HDL] Add digital I/O self testing testbench 2020-12-11 16:11:12 -07:00
tangxifan 52d98eb7ca [HDL] Revert I/O cell back to the current design in GDS 2020-12-11 11:26:46 -07:00
tangxifan 88f522026a [Doc] Update I/O schematic to be consistent with HDL netlist 2020-12-11 11:25:28 -07:00
tangxifan 9dc1b6efa7 [Doc] Fine tune documentation on I/O design 2020-12-11 11:25:07 -07:00
tangxifan c1cdca61b5 [HDL] Critical Patch on the digital I/O cell which now outputs 'Z' when input mode is selected 2020-12-11 10:59:28 -07:00
tangxifan 00b1740b44
Merge pull request #65 from lnis-uofu/xt_dev 
Bug fix in the custom cell code generator
 2020-12-11 10:12:53 -07:00
tangxifan 9c80a1b1a7 [HDL] Bug fix in the custom cell code generator 2020-12-10 15:45:20 -07:00
tangxifan 3ccb0e2931
Merge pull request #64 from lnis-uofu/xt_dev 
Release of Testbenches for SOFA CHD version and Documentation Update
 2020-12-09 20:55:06 -07:00
tangxifan b1a606443f [Doc] Add motiviation figure and reworked introduction part 2020-12-09 20:12:09 -07:00
tangxifan abd51929f9 [Doc] Add MUX design information to documentation 2020-12-09 17:51:15 -07:00
tangxifan 9f82ac7636 [Doc] Add SOFA CHD to documentation. Clean up redundant document between HD FPGA IPs 2020-12-09 16:18:04 -07:00
tangxifan d9e965cf3b [Testbench] Add post-PnR testbenches for SOFA-CHD 2020-12-09 14:55:27 -07:00
tangxifan 5a567644db
Merge pull request #63 from lnis-uofu/xt_dev 
Fine-tune architecture file to be consistent in port naming of SOFA CHD
 2020-12-09 14:05:20 -07:00
tangxifan e7fd8e7d92 [Arch] Fine-tune architecture file to be consistent in port naming as post-PnR netlist 2020-12-09 12:12:40 -07:00
tangxifan 73622b1df5 [TESTBENCH] Add more cells that are used by post-PNR CHD FPGA 2020-12-09 12:12:14 -07:00
tangxifan 0c761ebc05
Merge pull request #61 from lnis-uofu/ganesh_dev 
SOFA CHD Post-PnR Netlist
 2020-12-09 10:41:29 -07:00
tangxifan 0180a5146f
Merge pull request #62 from lnis-uofu/xt_dev 
Bug fix on the CI dependency for OpenFPGA-run in Github Actions
 2020-12-09 09:53:45 -07:00
Ganesh Gore d9b945ab6f [Actions] Temporarily disable deployment 
+ Magic DRC check fails on CI machine
+ Not enough RAM
+ Will perform test locally and upload
 2020-12-09 01:04:26 -07:00
Ganesh Gore 77bb6d4eae [SOFA_CHD] Added Verification results 2020-12-09 00:55:27 -07:00
Ganesh Gore 45ff6d2dfe [SOFA_CHD] Added post-pnr netlist, Verified CCFF/SCFF 2020-12-09 00:54:03 -07:00
Ganesh Gore 1a2e6de718 [SOFA_CHD] Removed large testbench file 2020-12-09 00:51:30 -07:00
Ganesh Gore 9284bbf8fa [SOFA_CHD] Added OpenFPGA taks and verilog netlist 2020-12-09 00:49:00 -07:00
Ganesh Gore def270a94b [Actions] Launched checker in correct directory 2020-12-08 21:50:18 -07:00
tangxifan 3c9017b2f8 [CI] Bug fix 2020-12-08 16:41:22 -07:00
tangxifan 80937ca769 [CI] Update dependency to sync with OpenFPGA 2020-12-08 16:36:02 -07:00
tangxifan ed92cba451 [HDL] Add netlist for simulation with Caravel + FPGA 2020-12-08 15:35:38 -07:00
Ganesh Gore 3ecd96596f [Actions] Merged Caravel with Klayout 2020-12-08 13:33:17 -07:00
Laboratory for Nano Integrated Systems (LNIS) 06ea86c0b0
Merge pull request #60 from lnis-uofu/xt_dev 
Scripts to Automate the Synthesis for the decoders in FPGAs with custom cells
 2020-12-08 13:30:40 -07:00
Ganesh Gore 2f2b301395 [Action] Updated repo destination 2020-12-08 11:31:04 -07:00
Ganesh Gore 9efe8a7935 [Actions] Added correct repository 2020-12-08 10:24:54 -07:00
tangxifan 3cc54ccb59 [MSIM] Bug fix 2020-12-08 10:15:39 -07:00
tangxifan 4247819ccb Merge branch 'xt_dev' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev 2020-12-08 10:13:33 -07:00
tangxifan 55ff90905f [DC] Add scripts to automate the synthesis for local encoders 2020-12-08 10:12:57 -07:00
tangxifan 3d2f792fa5
Merge pull request #59 from lnis-uofu/xt_dev 
Now modelsim verification is multithreaded
 2020-12-07 18:53:42 -07:00
tangxifan 77dfb469b5
Update MSIM/common/run_post_pnr_msim_task.py 
Co-authored-by: Ashton Snelgrove <ashton.snelgrove@utah.edu>
 2020-12-07 17:41:22 -07:00
tangxifan 7f9c8e2e90 [Doc] Add Readme for design compiler workspace 2020-12-07 17:40:08 -07:00
tangxifan 2f741ecc15 [MSIM] Now modelsim verification is multithreaded 2020-12-07 15:25:48 -07:00
Ganesh Gore 0e691fe9ca [SOFA-HD] Updated reports and screenshots 2020-12-07 11:55:59 -07:00
Ganesh Gore 40f1e1fae1 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-07 10:14:56 -07:00
Laboratory for Nano Integrated Systems (LNIS) 67e0c94c66
Merge pull request #58 from lnis-uofu/xt_dev 
Scripts for Verifications on Custom Cell -based FPGA (SOFA CHD)
 2020-12-07 09:45:43 -07:00