tangxifan
|
be98775ae5
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[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
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2021-04-28 10:45:10 -06:00 |
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tangxifan
|
5c729657ef
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[Test] Bug fix in test case for DPRAM whose width = 2
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2021-04-28 10:31:22 -06:00 |
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tangxifan
|
79b27a6329
|
[Arch] Patch arch using DPRAM block with wide = 2
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2021-04-28 10:29:09 -06:00 |
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tangxifan
|
63309ba72b
|
[HDL] Patch dpram cell
|
2021-04-27 23:42:31 -06:00 |
|
tangxifan
|
411af10933
|
[Script] Patch yosys script for 16kbit dual port RAM
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2021-04-27 23:41:47 -06:00 |
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tangxifan
|
834657f2da
|
[Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes
|
2021-04-27 23:41:14 -06:00 |
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tangxifan
|
0bec4b3f32
|
[Test] Update task configuration to use proper openfpgashell script
|
2021-04-27 23:34:42 -06:00 |
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tangxifan
|
7d059f7407
|
[Benchmark] Bug fix in dual port ram 16k benchmark
|
2021-04-27 23:33:20 -06:00 |
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tangxifan
|
3c1c33bf1e
|
[Benchmark] Add a microbenchmark just fit 16k dual port ram
|
2021-04-27 22:51:43 -06:00 |
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tangxifan
|
7e2368158e
|
[Benchmark] move benchmarks to microbenchmark category
|
2021-04-27 22:12:30 -06:00 |
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tangxifan
|
5a85ec9fa0
|
[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
|
2021-04-27 22:09:10 -06:00 |
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tangxifan
|
dd46780865
|
[Script] Update yosys script using BRAMs
|
2021-04-27 21:44:27 -06:00 |
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tangxifan
|
fdfbdc4613
|
[Test] Update task configuration files to use dedicated yosys script
|
2021-04-27 20:05:04 -06:00 |
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tangxifan
|
2802b0895c
|
[HDL] Add yosys technology library for reworked architecture using 16k-bit DPRAM
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2021-04-27 19:55:46 -06:00 |
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tangxifan
|
e67095edd2
|
[HDL] Add 16k-bit dual port ram verilog
|
2021-04-27 19:55:16 -06:00 |
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tangxifan
|
0f8aaae2bc
|
[Arch] Patch architecture using 16kbit dual port RAM
|
2021-04-27 19:54:34 -06:00 |
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tangxifan
|
1d498bb296
|
[Benchmark] Add a scalable micro benchmark fifo
|
2021-04-27 15:26:52 -06:00 |
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tangxifan
|
6cb4d7d720
|
[Test] Add the new test to regressiont test
|
2021-04-27 14:41:38 -06:00 |
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tangxifan
|
b8ced5377f
|
[Test] Add a test case for i/o mapping writer
|
2021-04-27 14:41:15 -06:00 |
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tangxifan
|
f9fd444b86
|
[Script] Add an write I/O mapping example script for openfpga shell
|
2021-04-27 14:40:26 -06:00 |
|
tangxifan
|
1d5e926d9e
|
[Test] Deploy new test to CI
|
2021-04-26 16:29:54 -06:00 |
|
tangxifan
|
6291871faf
|
[Test] Added a test for the example architecture with 2x2 DSP blocks
|
2021-04-26 16:28:43 -06:00 |
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tangxifan
|
8c007c7c49
|
[Arch] Add a new example architecture where a DSP block occupies a 2x2 grid
|
2021-04-26 16:28:10 -06:00 |
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tangxifan
|
7d4c5e3cd1
|
[Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block
|
2021-04-26 12:00:57 -06:00 |
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tangxifan
|
6e87b8875b
|
[Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block
|
2021-04-26 11:59:25 -06:00 |
|
tangxifan
|
b7da22501c
|
[Test] Deply new test to regression test
|
2021-04-24 15:55:05 -06:00 |
|
tangxifan
|
5adffad602
|
[Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!!
|
2021-04-24 15:49:53 -06:00 |
|
tangxifan
|
80f98328df
|
[Test] Update test settings for architecture with fracturable DSP blocks
|
2021-04-24 15:16:50 -06:00 |
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tangxifan
|
8b8096f3a8
|
[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block
|
2021-04-24 14:57:09 -06:00 |
|
tangxifan
|
a3a98fa21d
|
[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition
|
2021-04-24 14:56:10 -06:00 |
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tangxifan
|
4f454abfde
|
[Arch] Add a new architecture using fracturable 16-bit DSP blocks
|
2021-04-24 14:01:42 -06:00 |
|
tangxifan
|
272d1fffb7
|
[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks
|
2021-04-24 13:30:46 -06:00 |
|
tangxifan
|
ddcdb35b28
|
[Arch] Bug fix in single-mode 8-bit DSP architectures
|
2021-04-24 13:30:03 -06:00 |
|
tangxifan
|
1c6b9a23d7
|
[Test] Add new test for multi-mode 16-bit DSP blocks
|
2021-04-24 13:29:29 -06:00 |
|
tangxifan
|
c44688739d
|
[HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks
|
2021-04-23 22:12:26 -06:00 |
|
tangxifan
|
09cc7f0007
|
[Script] Enable constant net routing for heterogeneous FPGAs
|
2021-04-23 20:44:36 -06:00 |
|
tangxifan
|
189c94ff19
|
[Test] Deploy new mac benchmarks to tests
|
2021-04-23 20:44:14 -06:00 |
|
tangxifan
|
200b6d39a6
|
[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit
|
2021-04-23 20:36:28 -06:00 |
|
tangxifan
|
671394ec2c
|
[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing
|
2021-04-23 20:33:43 -06:00 |
|
tangxifan
|
cbb7d41b6e
|
[Script] Enable constant net routing for VTR benchmarks
|
2021-04-23 14:15:13 -06:00 |
|
tangxifan
|
784713e88a
|
[Test] Add golden results for IWLS2005 as a simple QoR check
|
2021-04-22 19:27:31 -06:00 |
|
tangxifan
|
a16896054d
|
[Script] Enable constant net routing for iwls benchmarks
|
2021-04-22 19:16:32 -06:00 |
|
tangxifan
|
1dcb8e39a9
|
[Test] Unlock more IWLS'2005 benchmarks in testing
|
2021-04-22 09:23:33 -06:00 |
|
tangxifan
|
61a473e479
|
[Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support
|
2021-04-21 22:56:19 -06:00 |
|
tangxifan
|
5a519390ff
|
[HDL] Enriched DFF model in yosys technology library
|
2021-04-21 22:49:05 -06:00 |
|
tangxifan
|
ce6018e123
|
[Arch] Enriched DFF model to support active-low/high FFs
|
2021-04-21 22:48:31 -06:00 |
|
tangxifan
|
adfea88be2
|
[HDL] Rename multi-mode DFF module
|
2021-04-21 20:06:03 -06:00 |
|
tangxifan
|
62497549b6
|
[HDL] Add multi-mode DFF module
|
2021-04-21 20:04:40 -06:00 |
|
tangxifan
|
3a5c26c6a1
|
[Test] Update IWLS test by using new architecture and customize DFF techmap
|
2021-04-21 19:51:25 -06:00 |
|
tangxifan
|
8cbea6a268
|
[HDL] Add technology library for customizable DFF synthesis
|
2021-04-21 19:50:51 -06:00 |
|
tangxifan
|
3d615e1516
|
[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping
|
2021-04-21 19:50:07 -06:00 |
|
tangxifan
|
9d9840d9b7
|
[Arch] Add architecture using multi-mode DFFs
|
2021-04-21 19:49:48 -06:00 |
|
tangxifan
|
8046b16c15
|
[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
|
2021-04-21 14:04:34 -06:00 |
|
tangxifan
|
b203ef7bc2
|
[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
|
2021-04-21 14:03:51 -06:00 |
|
tangxifan
|
2fa370d7d5
|
[Test] Patch regression tests for fpga bitstream
|
2021-04-19 17:15:14 -06:00 |
|
tangxifan
|
64163edbe6
|
[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
|
2021-04-19 16:15:25 -06:00 |
|
tangxifan
|
578d81b67a
|
[Test] Patch task configuration file
|
2021-04-19 16:15:00 -06:00 |
|
tangxifan
|
18eb5c9de9
|
[Test] Deploy new test to CI
|
2021-04-19 15:56:41 -06:00 |
|
tangxifan
|
5976cc0a1c
|
[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
|
2021-04-19 15:54:18 -06:00 |
|
tangxifan
|
7018073e28
|
[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
|
2021-04-17 15:04:51 -06:00 |
|
tangxifan
|
da95da933b
|
[Test] Add pin constraint file to map reset to correct FPGA pins
|
2021-04-17 15:04:26 -06:00 |
|
tangxifan
|
e3dafe99da
|
[Arch] Revert to old version arch due to editing by mistake
|
2021-04-16 20:58:32 -06:00 |
|
tangxifan
|
c020333512
|
Merge branch 'master' into dff_techmap
|
2021-04-16 20:54:28 -06:00 |
|
tangxifan
|
7172fc9ea1
|
[Test] Patch test for architecture using asynchronous DFFs
|
2021-04-16 20:48:37 -06:00 |
|
tangxifan
|
0a15f366cb
|
[HDL] Patch dff models used in yosys tech map
|
2021-04-16 20:48:15 -06:00 |
|
tangxifan
|
16e02ef485
|
[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
|
2021-04-16 20:47:39 -06:00 |
|
tangxifan
|
1c2f91b7e6
|
[Script] Patch yosys script with dff tech map
|
2021-04-16 20:47:18 -06:00 |
|
tangxifan
|
2666726f36
|
[Script] Remove clock routing from example openfpga shell script without ace
|
2021-04-16 20:46:49 -06:00 |
|
tangxifan
|
23d08757cf
|
[Script] Add example script without using ACE2
|
2021-04-16 20:20:10 -06:00 |
|
tangxifan
|
bbdc0e53af
|
[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
|
2021-04-16 20:14:48 -06:00 |
|
tangxifan
|
b11d03f9c5
|
[Test] Deploy new test to CI
|
2021-04-16 20:01:40 -06:00 |
|
tangxifan
|
93be81abe1
|
[Test] Add test case for architecture using DFF with reset
|
2021-04-16 20:00:48 -06:00 |
|
tangxifan
|
5414a6a3da
|
[Script] Add yosys script with custom DFF tech mapping
|
2021-04-16 20:00:30 -06:00 |
|
tangxifan
|
4239bb4e68
|
[Arch] Patch architecture files using multi-mode DFFs
|
2021-04-16 19:59:55 -06:00 |
|
tangxifan
|
f2f7f010ea
|
[Arch] Add new architectures using DFF with reset in VPR
|
2021-04-16 19:26:18 -06:00 |
|
tangxifan
|
64294ae4eb
|
[Doc] Update README for architecture files due to new architecture features
|
2021-04-16 19:25:54 -06:00 |
|
tangxifan
|
ff4460695b
|
[HDL] Add dff tech map files for yosys
|
2021-04-16 17:00:55 -06:00 |
|
tangxifan
|
e46c6e75a3
|
[Benchmark] Add missing RTL for IWLS2005 benchmarks
|
2021-04-16 16:50:41 -06:00 |
|
tangxifan
|
87587bbb74
|
[Test] Add iwls2005 benchmarks to regression tests
|
2021-04-16 16:12:05 -06:00 |
|
tangxifan
|
1566a5558a
|
[Test] Add task configuration file for iwls2005
|
2021-04-16 16:10:31 -06:00 |
|
tangxifan
|
43bf016576
|
[Script] Add example openfpga shell script for iwls benchmark
|
2021-04-16 16:09:47 -06:00 |
|
tangxifan
|
26d3b5a954
|
[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
|
2021-04-16 16:08:58 -06:00 |
|
tangxifan
|
86ad572530
|
[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
|
2021-04-16 14:27:54 -06:00 |
|
tangxifan
|
b469705819
|
Merge branch 'master' into fpga_sdc_test
|
2021-04-11 21:14:46 -06:00 |
|
tangxifan
|
1db8bd7eec
|
[Test] Update regression test with new SDC tests
|
2021-04-11 20:24:32 -06:00 |
|
tangxifan
|
07f6066c11
|
[Script] Update timing unit in SDC example script
|
2021-04-11 20:24:18 -06:00 |
|
tangxifan
|
94c4c817eb
|
[Test] Expand sdc time unit test to sweep all the available units
|
2021-04-11 20:14:09 -06:00 |
|
tangxifan
|
a4893e27cf
|
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
|
2021-04-11 17:26:27 -06:00 |
|
tangxifan
|
44d97ead86
|
Merge branch 'master' into hetergeneous_arch
|
2021-03-23 17:05:03 -06:00 |
|
tangxifan
|
b00b4f0f5f
|
[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
|
2021-03-23 15:44:53 -06:00 |
|
tangxifan
|
d82ffe0cbf
|
[Test] Deploy MAC_8 benchmark to regression test
|
2021-03-23 15:36:28 -06:00 |
|
tangxifan
|
108c84a022
|
[HDL] Add HDL for 8-bit single-mode multiplier
|
2021-03-23 15:36:09 -06:00 |
|
tangxifan
|
145a80de43
|
[Script] Add an openfpga shell script for heterogeneous fpga verification
|
2021-03-23 15:35:34 -06:00 |
|
tangxifan
|
fdec72b5bc
|
[Arch] Add an example architecture with 8-bit single-mode multiplier
|
2021-03-23 15:35:06 -06:00 |
|
tangxifan
|
be03eafd66
|
[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate
|
2021-03-23 15:33:37 -06:00 |
|
tangxifan
|
8c970a792a
|
[Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier
|
2021-03-23 15:33:00 -06:00 |
|
tangxifan
|
6b0409da60
|
[Script] Add a template yosys script support only DSP mapping
|
2021-03-23 15:32:10 -06:00 |
|
tangxifan
|
a4bbffd1aa
|
[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
|
2021-03-23 15:30:41 -06:00 |
|
tangxifan
|
fff16a01ab
|
[Test] Update tolerance when checking VTR benchmark QoR
|
2021-03-23 12:27:20 -06:00 |
|
tangxifan
|
781880ed93
|
[Script] Add tolerance options to check qor script
|
2021-03-23 12:26:33 -06:00 |