tangxifan
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ebab0e91ef
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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tangxifan
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5d507ae8ee
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bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
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2019-11-04 18:05:50 -07:00 |
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tangxifan
|
69bc858e62
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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tangxifan
|
3274a49779
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fine tuning top testbench and getting ready for testing
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2019-11-04 12:08:36 -07:00 |
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tangxifan
|
d7bbae76a4
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adding stimuli to benchmark inputs in top-level testbench
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2019-11-03 20:20:14 -07:00 |
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tangxifan
|
3e9968d2f0
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keep refactoring top-level testbench with auto-check features
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2019-11-03 18:59:54 -07:00 |
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tangxifan
|
1fb29df1e2
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cleaning verilog file lines
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2019-11-03 17:58:18 -07:00 |
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tangxifan
|
0ec465d4e1
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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tangxifan
|
dc241e6c03
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add explicit port mapping support in testbenches; remove dangling ports in benchmarks
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2019-11-02 23:03:47 -06:00 |
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tangxifan
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05a830de1b
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bring ini writer for formality scripts back
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2019-11-02 18:56:54 -06:00 |
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tangxifan
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c681726124
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try to enlarge write buffers in ini writer, but these codes should be fully reworked
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2019-11-02 18:33:05 -06:00 |
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tangxifan
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3ad2a93539
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start bring back ini writer bit by bit
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2019-11-02 18:20:25 -06:00 |
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tangxifan
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cb74d120e7
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shadow ini writer to help debugging
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2019-11-02 17:31:05 -06:00 |
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tangxifan
|
fc164abd49
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remove unused variable in sim info writer
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2019-11-02 16:35:32 -06:00 |
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tangxifan
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e1a7a2895a
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simulation ini file name can be customizable
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2019-11-02 09:59:34 -06:00 |
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tangxifan
|
d5d7450ce7
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make simulation ini writing as an option
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2019-11-02 09:46:12 -06:00 |
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tangxifan
|
c3db880599
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adding explicit file path to simulation info writer
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2019-11-02 09:21:02 -06:00 |
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tangxifan
|
358e9892ac
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reduce some error message to warnings
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2019-11-02 00:09:13 -06:00 |
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tangxifan
|
f70f387f9f
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minor tuning on ini compilation
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2019-11-01 20:51:49 -06:00 |
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tangxifan
|
3669a47d3b
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reworked the ini writer
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2019-11-01 20:25:01 -06:00 |
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tangxifan
|
dab66b8be7
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start adding auto check cpp files
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2019-11-01 19:49:50 -06:00 |
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tangxifan
|
e2b042c61c
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-11-01 18:27:27 -06:00 |
Ganesh Gore
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a0512e40b1
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Created intermidiate file for modelsim simulation
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2019-11-01 18:20:00 -06:00 |
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tangxifan
|
3ae841b80f
|
start refactoring auto-check top testbench generation
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2019-11-01 16:33:12 -06:00 |
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tangxifan
|
531cc064fc
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bug fixing for formal top-level testbench
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2019-11-01 10:47:40 -06:00 |
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Ganesh Gore
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da0778e813
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Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
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2019-11-01 00:46:34 -06:00 |
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tangxifan
|
2dff779005
|
critical bug fixed for bitstream generation for offset truth tables
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2019-10-31 20:16:08 -06:00 |
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tangxifan
|
a6a3e7c36b
|
adding mcnc_big20 to regression test
|
2019-10-31 19:31:27 -06:00 |
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tangxifan
|
858c1aefce
|
try use force for Icarus
|
2019-10-30 19:50:34 -06:00 |
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tangxifan
|
7460dc8cab
|
pass current regression tests
|
2019-10-30 19:10:36 -06:00 |
|
tangxifan
|
55fbd72293
|
many bugs have been fixed
|
2019-10-30 15:50:42 -06:00 |
|
tangxifan
|
4398cffaaa
|
single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
|
1faacfa3cf
|
keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine
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2019-10-29 14:23:09 -06:00 |
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tangxifan
|
7c116aac2f
|
added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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tangxifan
|
10491c4291
|
bring single mode test case online with bug fixing
|
2019-10-28 17:04:10 -06:00 |
|
tangxifan
|
fe005f1f56
|
remove legacy codes for Verilog formal verification testbench generation
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2019-10-28 15:21:14 -06:00 |
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tangxifan
|
c047fd3cb2
|
plugged in the refactored formal verification Verilog testbench using random vectors
|
2019-10-28 15:10:29 -06:00 |
|
tangxifan
|
ccabe4ce2a
|
refactoring Verilog formal verification top testbench using random vectors
|
2019-10-28 14:45:51 -06:00 |
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tangxifan
|
55eea6c4d5
|
rename files to be clear
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2019-10-27 20:12:48 -06:00 |
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tangxifan
|
35073f48cf
|
add runtime profiling to module graph builders
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2019-10-27 19:10:21 -06:00 |
|
tangxifan
|
2b06cfc3cf
|
added fabric bitstream generator and fixed critical bugs in top module graph
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2019-10-27 18:47:33 -06:00 |
|
tangxifan
|
f116351831
|
add instance name for each pb graph node
|
2019-10-26 17:25:45 -06:00 |
|
tangxifan
|
7649d9228e
|
fixed bugs in refactored bitstream generation
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2019-10-26 16:40:14 -06:00 |
|
tangxifan
|
0a9c89be0b
|
add bitstream writers and start debugging
|
2019-10-26 12:41:23 -06:00 |
|
tangxifan
|
3310bac65b
|
refactored grid bitstream generation
|
2019-10-25 21:49:47 -06:00 |
|
tangxifan
|
4b7a9dfa63
|
add instance name correlation between module and bitstream generation
|
2019-10-25 13:06:48 -06:00 |
|
tangxifan
|
0b687669c8
|
affliate configuration bitstream to sb blocks
|
2019-10-25 10:42:12 -06:00 |
|
tangxifan
|
c38513c838
|
add local encoder support in bitstream generation refactoring
|
2019-10-24 22:49:24 -06:00 |
|
tangxifan
|
97193794c4
|
correct bugs in organizing child modules in top-level module
|
2019-10-24 21:27:42 -06:00 |
|
tangxifan
|
838173f3c4
|
start refactoring bitstream generator
|
2019-10-24 21:01:11 -06:00 |