tangxifan
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ebab0e91ef
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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tangxifan
|
5d507ae8ee
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bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
|
2019-11-04 18:05:50 -07:00 |
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tangxifan
|
69bc858e62
|
bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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tangxifan
|
3274a49779
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fine tuning top testbench and getting ready for testing
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2019-11-04 12:08:36 -07:00 |
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tangxifan
|
d7bbae76a4
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adding stimuli to benchmark inputs in top-level testbench
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2019-11-03 20:20:14 -07:00 |
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tangxifan
|
3e9968d2f0
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keep refactoring top-level testbench with auto-check features
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2019-11-03 18:59:54 -07:00 |
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tangxifan
|
1fb29df1e2
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cleaning verilog file lines
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2019-11-03 17:58:18 -07:00 |
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tangxifan
|
0ec465d4e1
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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tangxifan
|
dc241e6c03
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add explicit port mapping support in testbenches; remove dangling ports in benchmarks
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2019-11-02 23:03:47 -06:00 |
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tangxifan
|
05a830de1b
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bring ini writer for formality scripts back
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2019-11-02 18:56:54 -06:00 |
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tangxifan
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c681726124
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try to enlarge write buffers in ini writer, but these codes should be fully reworked
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2019-11-02 18:33:05 -06:00 |
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tangxifan
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3ad2a93539
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start bring back ini writer bit by bit
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2019-11-02 18:20:25 -06:00 |
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tangxifan
|
644ca4f0a4
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add vpr test run in Travis
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2019-11-02 17:49:22 -06:00 |
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tangxifan
|
cb74d120e7
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shadow ini writer to help debugging
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2019-11-02 17:31:05 -06:00 |
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tangxifan
|
fc164abd49
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remove unused variable in sim info writer
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2019-11-02 16:35:32 -06:00 |
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tangxifan
|
0852ef33c3
|
remove caching for deps
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2019-11-02 16:30:01 -06:00 |
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tangxifan
|
e1a7a2895a
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simulation ini file name can be customizable
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2019-11-02 09:59:34 -06:00 |
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tangxifan
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d5d7450ce7
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make simulation ini writing as an option
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2019-11-02 09:46:12 -06:00 |
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tangxifan
|
c3db880599
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adding explicit file path to simulation info writer
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2019-11-02 09:21:02 -06:00 |
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tangxifan
|
358e9892ac
|
reduce some error message to warnings
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2019-11-02 00:09:13 -06:00 |
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tangxifan
|
5bae8fecde
|
add debugging mode to see why travis failed
|
2019-11-01 23:26:08 -06:00 |
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tangxifan
|
495000c649
|
recover caching for libs
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2019-11-01 21:37:17 -06:00 |
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tangxifan
|
17f816effd
|
try to uncache libini
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2019-11-01 21:26:22 -06:00 |
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tangxifan
|
e9ed64c926
|
try to let cmake identify libini
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2019-11-01 21:17:35 -06:00 |
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tangxifan
|
f811ddc62a
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-11-01 20:52:45 -06:00 |
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tangxifan
|
f70f387f9f
|
minor tuning on ini compilation
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2019-11-01 20:51:49 -06:00 |
Ganesh Gore
|
a880802803
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Bug Fix: Corrected read VPR stat filename
|
2019-11-01 20:51:05 -06:00 |
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tangxifan
|
a9c02cd2a5
|
fix errors in travis
|
2019-11-01 20:32:40 -06:00 |
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tangxifan
|
550df19ee2
|
use a stable cmake now
|
2019-11-01 20:26:29 -06:00 |
|
tangxifan
|
3669a47d3b
|
reworked the ini writer
|
2019-11-01 20:25:01 -06:00 |
|
tangxifan
|
dab66b8be7
|
start adding auto check cpp files
|
2019-11-01 19:49:50 -06:00 |
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tangxifan
|
e2b042c61c
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-11-01 18:27:27 -06:00 |
|
Ganesh Gore
|
370a5ed408
|
Bug Fix: shifter ff.v include path to tcl script
|
2019-11-01 18:22:40 -06:00 |
|
Ganesh Gore
|
595d2d3070
|
Simple argument shuffle
|
2019-11-01 18:21:26 -06:00 |
|
Ganesh Gore
|
27005d6640
|
Added Modelsim Python Script
|
2019-11-01 18:20:40 -06:00 |
|
Ganesh Gore
|
a0512e40b1
|
Created intermidiate file for modelsim simulation
|
2019-11-01 18:20:00 -06:00 |
|
tangxifan
|
4d4ef1113d
|
give up iverilog on travis
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2019-11-01 17:53:50 -06:00 |
|
tangxifan
|
1d78725d4d
|
add installation
|
2019-11-01 17:48:17 -06:00 |
|
tangxifan
|
9a37b66d53
|
move installation to a script
|
2019-11-01 17:39:30 -06:00 |
|
tangxifan
|
161664f253
|
try to comfort iverilog package extraction
|
2019-11-01 17:24:06 -06:00 |
|
tangxifan
|
2dc3a4eb1f
|
fixing bugs in iVerilog installation
|
2019-11-01 17:03:21 -06:00 |
|
tangxifan
|
5332588e82
|
retrying travis installation of iVerilog 10.3
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2019-11-01 16:36:29 -06:00 |
|
tangxifan
|
3ae841b80f
|
start refactoring auto-check top testbench generation
|
2019-11-01 16:33:12 -06:00 |
|
tangxifan
|
b61b81b8d8
|
tuning iverilog version display
|
2019-11-01 15:29:08 -06:00 |
|
tangxifan
|
d4fedb76d7
|
revert to default iverilog of Ubuntu 18.04
|
2019-11-01 15:24:58 -06:00 |
|
tangxifan
|
b54bec1609
|
streamline regression tes
|
2019-11-01 15:23:38 -06:00 |
|
tangxifan
|
000f93ffd7
|
try to fix travis bugs
|
2019-11-01 15:19:34 -06:00 |
|
tangxifan
|
480478e545
|
reorganizing travis
|
2019-11-01 15:12:08 -06:00 |
|
tangxifan
|
8c0d60abd6
|
debugging travis
|
2019-11-01 15:00:33 -06:00 |
|
tangxifan
|
c2cef205a4
|
update travis: try to compile iverilog through source
|
2019-11-01 14:52:42 -06:00 |