ANDREW HARRIS POND
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8513b8a4ff
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Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
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2021-07-01 15:29:39 -06:00 |
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ANDREW HARRIS POND
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2567fbee05
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ready to merge
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2021-07-01 15:28:59 -06:00 |
tangxifan
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04ceeefb0a
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Merge branch 'master' into verilog_testbench
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2021-07-01 14:43:26 -06:00 |
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ANDREW HARRIS POND
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db9231c225
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tests failing with initial blocks
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2021-07-01 13:52:28 -06:00 |
Andrew Pond
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fab2b069f0
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added signal gen regression test to shell script
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2021-06-30 16:18:09 -06:00 |
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tangxifan
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cbea4a3cb6
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[Test] Add the test cases to regression test
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2021-06-29 16:08:22 -06:00 |
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tangxifan
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b4c587f10b
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[Test] Added the new test cases to regression tests
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2021-06-27 19:58:15 -06:00 |
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tangxifan
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477cba1c7e
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Merge branch 'master' into verilog_testbench
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2021-06-23 09:18:18 -06:00 |
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tangxifan
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e34fbf8ecf
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[Test] Deploy MCNC big20 to the micro benchmark regression test
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2021-06-22 16:36:04 -06:00 |
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tangxifan
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0b2d6eb147
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[Test] Add micro benchmark to a dedicated regression test
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2021-06-21 18:35:41 -06:00 |
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Andrew Pond
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3cfc42cdf9
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added testbench CI
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2021-06-15 14:16:31 -06:00 |
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tangxifan
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c33ca464dc
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[Test] Deploy new tests to regression test
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2021-05-07 12:06:46 -06:00 |
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tangxifan
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a5e40fbb21
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Merge branch 'master' into micro_benchmarks
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2021-04-28 14:27:58 -06:00 |
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tangxifan
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870432e7f1
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[Test] Patch regression test script due to the change of DPRAM test case
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2021-04-28 12:45:52 -06:00 |
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tangxifan
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6cb4d7d720
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[Test] Add the new test to regressiont test
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2021-04-27 14:41:38 -06:00 |
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tangxifan
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1d5e926d9e
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[Test] Deploy new test to CI
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2021-04-26 16:29:54 -06:00 |
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tangxifan
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b7da22501c
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[Test] Deply new test to regression test
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2021-04-24 15:55:05 -06:00 |
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tangxifan
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784713e88a
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[Test] Add golden results for IWLS2005 as a simple QoR check
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2021-04-22 19:27:31 -06:00 |
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tangxifan
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2fa370d7d5
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[Test] Patch regression tests for fpga bitstream
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2021-04-19 17:15:14 -06:00 |
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tangxifan
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18eb5c9de9
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[Test] Deploy new test to CI
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2021-04-19 15:56:41 -06:00 |
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tangxifan
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c020333512
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Merge branch 'master' into dff_techmap
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2021-04-16 20:54:28 -06:00 |
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tangxifan
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b11d03f9c5
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[Test] Deploy new test to CI
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2021-04-16 20:01:40 -06:00 |
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tangxifan
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87587bbb74
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[Test] Add iwls2005 benchmarks to regression tests
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2021-04-16 16:12:05 -06:00 |
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tangxifan
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1db8bd7eec
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[Test] Update regression test with new SDC tests
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2021-04-11 20:24:32 -06:00 |
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tangxifan
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44d97ead86
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Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
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tangxifan
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d82ffe0cbf
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[Test] Deploy MAC_8 benchmark to regression test
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2021-03-23 15:36:28 -06:00 |
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tangxifan
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fff16a01ab
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[Test] Update tolerance when checking VTR benchmark QoR
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2021-03-23 12:27:20 -06:00 |
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tangxifan
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e3f8a6cf7a
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[Test] Deploy QoR check to VTR benchmark regression test
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2021-03-23 11:15:22 -06:00 |
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tangxifan
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08a86e056a
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[Test] Add vtr benchmark regression test
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2021-03-17 15:13:58 -06:00 |
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tangxifan
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e34380a654
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Merge branch 'master' into default_net_type
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2021-03-01 08:38:58 -07:00 |
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tangxifan
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86930d63d3
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[Test] Deploy new test to CI
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2021-02-28 16:18:46 -07:00 |
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tangxifan
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6d419fed41
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[Test] Deploy verilog default net wire type test case to CI
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2021-02-28 12:33:48 -07:00 |
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tangxifan
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27200e3daa
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[Test] Update regression test cases for fpga verilog
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2021-02-28 12:24:36 -07:00 |
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tangxifan
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86a602d381
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[Test] Deploy new test to CI
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2021-02-23 19:55:07 -07:00 |
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tangxifan
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b3fed683f9
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[Test] Deploy test to CI
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2021-02-22 12:43:30 -07:00 |
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tangxifan
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e08ac1a41e
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[Test] Deploy synthesizable verilog test to CI
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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affc8cbbc4
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[Test] Deploy test to CI
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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2c2e493739
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[Test] Remove quicklogic test from basic tests
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2021-02-16 12:29:10 -07:00 |
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tangxifan
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9c19e2b365
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[Test] Move regression test scripts from workflow to openfpga_flow
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2021-02-16 11:55:47 -07:00 |