tangxifan
|
513f7800aa
|
[test] update golden outputs for no_cout_in_gsb testcase
|
2022-11-03 17:51:51 -07:00 |
|
tangxifan
|
a88bc2d4de
|
[test] update golden outputs for device4x4
|
2022-11-03 17:51:08 -07:00 |
|
tangxifan
|
5f74367c2e
|
[test] update golden for device1x1 no time stamp netlists
|
2022-11-03 17:48:40 -07:00 |
|
tangxifan
|
00a485cbeb
|
[test] add missing file
|
2022-10-17 19:44:25 -07:00 |
|
tangxifan
|
609e096b1a
|
[test] added a new test to validate explicit port direction in pin table support
|
2022-10-17 15:25:19 -07:00 |
|
tangxifan
|
8b00bfdff9
|
[test] replace hardcoded paths in task config files with relative paths
|
2022-10-17 11:55:57 -07:00 |
|
tangxifan
|
aa78981e37
|
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
|
2022-10-17 11:18:21 -07:00 |
|
tangxifan
|
b0be27b384
|
[test] add repack design constraints files
|
2022-10-13 11:22:48 -07:00 |
|
tangxifan
|
7f67794787
|
[arch]add new arch to test
|
2022-10-13 10:54:40 -07:00 |
|
tangxifan
|
4eaecde0b9
|
[test] add golden netlists to ensure no cout in gsb
|
2022-10-01 11:03:13 -07:00 |
|
tangxifan
|
78f30cf072
|
[test] add a new test to track the golden netlists where cout is not in GSB
|
2022-09-30 15:38:27 -07:00 |
|
tangxifan
|
3f8e2ade2e
|
[script] update missing scripts required by pb_pin_fixup test cases
|
2022-09-29 13:39:46 -07:00 |
|
tangxifan
|
49fa783914
|
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
|
2022-09-29 10:45:27 -07:00 |
|
tangxifan
|
b532bca9d2
|
[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
|
2022-09-21 10:54:16 -07:00 |
|
tangxifan
|
36603f9772
|
Merge branch 'master' into vtr_upgrade
|
2022-09-20 21:08:06 -07:00 |
|
tangxifan
|
b8f1520367
|
[test] fixed a bug
|
2022-09-20 18:12:23 -07:00 |
|
tangxifan
|
4e254a304d
|
[test] now golden netlists have no relationship with OPENFPGA_PATH
|
2022-09-20 18:10:52 -07:00 |
|
tangxifan
|
5e23be19a5
|
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
|
2022-09-20 18:07:31 -07:00 |
|
tangxifan
|
1b0b50b928
|
[test] update golden netlist
|
2022-09-20 16:04:05 -07:00 |
|
tangxifan
|
846ca26311
|
[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
|
2022-09-20 12:08:24 -07:00 |
|
tangxifan
|
10e86d334a
|
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
|
2022-09-16 10:29:19 -07:00 |
|
tangxifan
|
330785635d
|
[test] now use a bigger fabric for the test case on custom I/O location
|
2022-09-13 17:53:33 -07:00 |
|
tangxifan
|
0d6e4e3979
|
[test] add a new example for the repack options
|
2022-09-12 16:21:49 -07:00 |
|
tangxifan
|
1ab7590603
|
[test] added a new test case to
|
2022-09-09 16:59:06 -07:00 |
|
tangxifan
|
d4523e819c
|
[test] fixed a bug
|
2022-09-08 16:55:50 -07:00 |
|
tangxifan
|
d76f3e3b6c
|
[test] fixed the bug
|
2022-09-08 16:34:23 -07:00 |
|
tangxifan
|
218e6d0a47
|
[arch] fixed syntax errors
|
2022-09-08 16:31:52 -07:00 |
|
tangxifan
|
a840aeea7a
|
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
|
2022-09-08 16:27:11 -07:00 |
|
tangxifan
|
477e2119d7
|
[test] remove abs paths in golden outputs without time stamps
|
2022-09-06 15:24:43 -07:00 |
|
tangxifan
|
93ab992187
|
[test] update golden outputs without time stamps
|
2022-09-06 14:59:00 -07:00 |
|
tangxifan
|
561d0a6545
|
[test] add more test case to track golden outputs for representative fpga sizes
|
2022-09-06 14:04:23 -07:00 |
|
tangxifan
|
51dc082bd4
|
[test] force a fixed routing chan W for no time stamp test case
|
2022-09-01 15:02:40 -07:00 |
|
tangxifan
|
d86eb04c5d
|
[test] now no timestamp test case covers gsb files
|
2022-09-01 14:03:51 -07:00 |
|
tangxifan
|
069e2b00b1
|
[test] add more test cases to validate gsb options
|
2022-08-29 22:03:06 -07:00 |
|
tangxifan
|
8b17bf1b1c
|
[test] add a new test case to validate that .act file is not required when power analysis flow is off
|
2022-08-01 18:44:47 -07:00 |
|
tangxifan
|
35fe858035
|
[test] fixed a few bugs
|
2022-07-28 12:06:16 -07:00 |
|
tangxifan
|
ca9122ddb9
|
[test] fixed a bug
|
2022-07-28 11:57:47 -07:00 |
|
tangxifan
|
ec31e124b7
|
[test] reworked test case on pcf2place
|
2022-07-28 11:51:56 -07:00 |
taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
|
tangxifan
|
6719a9aa26
|
[test] update golden netlists/testbenches etc.
|
2022-05-22 13:03:01 +08:00 |
|
tangxifan
|
22c4d72358
|
[test] add a test case to validate negative edge-triggered ff
|
2022-05-09 16:57:42 +08:00 |
|
tangxifan
|
efc25aa66e
|
[Script] Fixed a bug in wrong paths
|
2022-04-13 16:04:33 +08:00 |
|
tangxifan
|
5beefda3bd
|
[Test] Add a new test case to validate the fix_pins option
|
2022-04-13 15:55:21 +08:00 |
|
tangxifan
|
f8845f7d3a
|
[Test] Add a test case to validate separated clock pins in global port
|
2022-03-20 11:02:07 +08:00 |
|
tangxifan
|
fdaf97e60d
|
[Test] Update test case by using GPIO with config_done signals
|
2022-02-24 09:49:34 -08:00 |
|
tangxifan
|
a615c9d4e3
|
[Test] Rename test cases
|
2022-02-24 09:43:41 -08:00 |
|
tangxifan
|
b27a04eb24
|
[Test] Now test case has a config done CCFF
|
2022-02-23 22:07:11 -08:00 |
|
tangxifan
|
245c7b1e45
|
[Test] Add a new test case to validate config enable signal in preconfigured testbenches
|
2022-02-23 16:02:00 -08:00 |
|
tangxifan
|
e33ba667e4
|
[Test] Add missing file
|
2022-02-20 10:59:44 -08:00 |
|
tangxifan
|
f30de1085c
|
[Test] Cover all the related testcase about bus group
|
2022-02-19 23:33:16 -08:00 |
|
tangxifan
|
b4202f52b4
|
[Test] debugging
|
2022-02-19 23:26:29 -08:00 |
|
tangxifan
|
785bb1633d
|
[Test] trying to see if we support busgroup per benchmark in task configuration file
|
2022-02-19 23:23:36 -08:00 |
|
tangxifan
|
7645d5332d
|
[Test] Update bug group examples on the big endian support
|
2022-02-18 23:09:03 -08:00 |
|
tangxifan
|
f0ce1e79a3
|
[Test] Added a new test to validate bus group in full testbench
|
2022-02-18 15:43:21 -08:00 |
|
tangxifan
|
223575cf3e
|
[Test] Added a new test for bus group on full testbenches
|
2022-02-18 15:33:29 -08:00 |
|
tangxifan
|
5ab84e1861
|
[Test] Add a new test for bus group
|
2022-02-18 15:29:33 -08:00 |
|
tangxifan
|
b4d59fdd1e
|
[Test] Update bus group file due to little and big endian conversion during yosys/vpr
|
2022-02-18 15:02:08 -08:00 |
|
tangxifan
|
36543f7f2f
|
[Script] Support simplified rewriting for Yosys on output verilog
|
2022-02-18 14:54:39 -08:00 |
|
tangxifan
|
8ba3d06392
|
[Test] Fixed bugs in simulation settings
|
2022-02-18 12:36:22 -08:00 |
|
tangxifan
|
a4d5172b7c
|
[Test] Fixed bugs that causes VPR failed
|
2022-02-18 12:31:29 -08:00 |
|
tangxifan
|
7176037bc4
|
[Test] Added a new test about bus group
|
2022-02-18 12:26:00 -08:00 |
|
tangxifan
|
f002c79a61
|
[Test] Adapt pin constraints due to changes in pin names
|
2022-02-15 16:06:46 -08:00 |
|
tangxifan
|
b533fd17d5
|
[Test] Rework pin constraints that cause problems
|
2022-02-15 15:41:16 -08:00 |
|
tangxifan
|
9ef7ad64d8
|
[Test] Simplify paths
|
2022-02-15 15:35:21 -08:00 |
|
tangxifan
|
f8ef3df560
|
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
|
2022-01-26 11:41:48 -08:00 |
|
tangxifan
|
3b7588cd48
|
[Test] Rename test case to be consistent with the name of options
|
2022-01-26 11:25:54 -08:00 |
|
tangxifan
|
6b26ed0819
|
[Test] Add test cases on writing gsb files
|
2022-01-26 11:22:39 -08:00 |
|
tangxifan
|
23795d6474
|
[Test] Update golden netlists
|
2022-01-25 20:37:08 -08:00 |
|
tangxifan
|
a9e6b7c12e
|
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
|
2022-01-25 20:33:49 -08:00 |
|
tangxifan
|
fedb1bd2e3
|
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
|
2022-01-25 16:41:36 -08:00 |
|
tangxifan
|
6e778a74ee
|
[Test] Add golden reference for files outputted without time stamp
|
2022-01-25 16:24:25 -08:00 |
|
tangxifan
|
2bee59c6ca
|
[Test] Add the testcase to validate ``--no_time_stamp``
|
2022-01-25 16:21:15 -08:00 |
Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
397f2e71f1
|
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
|
2022-01-19 20:43:26 +05:00 |
|
Aram Kostanyan
|
588ee14920
|
Merge branch 'master' into issue-483
|
2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
Awais Abbas
|
598c5e6b75
|
Test case for yosys-only flow added
|
2022-01-14 15:37:47 +05:00 |
nadeemyaseen-rs
|
1ea56b2d18
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-18 00:00:55 +05:00 |
|
Aram Kostanyan
|
b332a5a1b4
|
Added 'basic_tests/verific_test' test-case.
|
2021-11-01 18:20:57 +05:00 |
|
tangxifan
|
b2c4e3314e
|
[Test] Bug fix in test cases
|
2021-10-11 10:28:09 -07:00 |
|
tangxifan
|
8566e2a0cd
|
[Test] Renaming test case to follow naming convention as other fabric key test cases
|
2021-10-11 09:56:23 -07:00 |
|
tangxifan
|
b8b02d37d5
|
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
|
2021-10-11 09:53:23 -07:00 |
|
tangxifan
|
6122863548
|
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
|
2021-10-09 20:44:28 -07:00 |
|
tangxifan
|
a1eaacf5a8
|
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
|
2021-10-06 12:12:15 -07:00 |
|
tangxifan
|
b98a8ec718
|
[Test] Added the dedicated test case for fixed shift register clock frequency
|
2021-10-06 12:09:26 -07:00 |
|
tangxifan
|
b21f212031
|
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
|
2021-10-05 11:39:53 -07:00 |
|
tangxifan
|
52569f808e
|
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
|
2021-10-05 10:57:33 -07:00 |
|
tangxifan
|
fa1908511d
|
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
|
2021-10-04 16:36:20 -07:00 |
|
tangxifan
|
dda147e234
|
[Flow] Add an example simulation setting file for defining programming shift register clocks
|
2021-10-01 11:04:23 -07:00 |
|
tangxifan
|
89a97d83bd
|
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
|
2021-09-29 16:28:06 -07:00 |
|
tangxifan
|
4400dae108
|
[Test] Bug fix in the wrong arch name
|
2021-09-28 11:40:25 -07:00 |
|
tangxifan
|
dae3554fd4
|
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
|
2021-09-28 11:27:49 -07:00 |
|
tangxifan
|
655b195d8b
|
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
|
2021-09-22 15:56:44 -07:00 |
|
tangxifan
|
b0aaab9c03
|
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
|
2021-09-22 11:32:13 -07:00 |
|
tangxifan
|
abfa380333
|
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
|
2021-09-22 11:27:09 -07:00 |
|
tangxifan
|
51fc222d61
|
[Test] Added a new test case for multi-region QL memory bank
|
2021-09-22 10:01:33 -07:00 |
|
tangxifan
|
1412121541
|
[Test] Added a new test to validate the fabric key parser for QL memory bank
|
2021-09-21 16:20:24 -07:00 |
|
tangxifan
|
dc2d1d1c3c
|
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
|
2021-09-21 15:42:20 -07:00 |
|
tangxifan
|
60fc3ab36c
|
[Test] Added a new test case for the WLR memory bank
|
2021-09-20 11:20:36 -07:00 |
|
tangxifan
|
b82cfdf555
|
[Test] Add the QL memory bank test to regression test cases
|
2021-09-09 09:29:21 -07:00 |