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OpenFPGA
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1060 Commits

Author SHA1 Message Date
tangxifan c6089385b0 [Misc] Bug fix 2021-06-29 18:34:41 -06:00
tangxifan 5f5a03f17f [Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches 2021-06-29 18:28:38 -06:00
tangxifan 2c1692e6dc [Test] Bug fix 2021-06-29 17:54:25 -06:00
tangxifan 4fb34642ca [Script] Add a new example script for global tile clock running full testbench 2021-06-29 17:53:56 -06:00
tangxifan 9655bc35cb [Script] Bug fix due to the full testbench generation changes 2021-06-29 17:04:19 -06:00
tangxifan cbea4a3cb6 [Test] Add the test cases to regression test 2021-06-29 16:08:22 -06:00
tangxifan 30c2f597f2 [Test] Added two cases to validate testbench generation without self checking 2021-06-29 16:06:15 -06:00
tangxifan 20faf82e64 [Script] Rename example script 2021-06-29 16:02:35 -06:00
tangxifan 01391fd81e [Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features 2021-06-29 15:56:33 -06:00
tangxifan 7119075253 [Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated 2021-06-29 15:52:42 -06:00
tangxifan 75a12e55de [HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes 2021-06-29 11:40:22 -06:00
tangxifan b4c587f10b [Test] Added the new test cases to regression tests 2021-06-27 19:58:15 -06:00
tangxifan 6f0600e17f [Test] Added two test cases for generating preconfigured fabric wrapper in different styles 2021-06-27 19:56:01 -06:00
tangxifan 4a623bec79 [Script] Add example openfpga shell script to generate preconfigured fabric wrapper 2021-06-27 19:55:40 -06:00
tangxifan fae5e1dfdf [Script] Upgrade openfpga shell script with the new option '--embed_bitstream' 2021-06-25 15:16:37 -06:00
tangxifan 477cba1c7e
Merge branch 'master' into verilog_testbench 2021-06-23 09:18:18 -06:00
tangxifan b2c30e3103 [Test] Bug fix in mcnc openfpga shell script 2021-06-22 16:40:24 -06:00
tangxifan e34fbf8ecf [Test] Deploy MCNC big20 to the micro benchmark regression test 2021-06-22 16:36:04 -06:00
tangxifan f06017581c [Test] Bug fix in counter micro benchmark tests 2021-06-22 16:33:50 -06:00
tangxifan 0a0d10b36d [HDL] Bug fix in Verilog syntax 2021-06-22 16:18:46 -06:00
tangxifan 4421dfcbbd
Merge branch 'master' into micro_benchmark 2021-06-22 14:29:29 -06:00
tangxifan fd580bb36f [Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name 2021-06-22 11:45:23 -06:00
tangxifan 0b2d6eb147 [Test] Add micro benchmark to a dedicated regression test 2021-06-21 18:35:41 -06:00
tangxifan 760570d883 [Test] Update counter test case for cover most counter HDL design 2021-06-21 18:13:18 -06:00
tangxifan 9c24a739be [Test] Added a MAC benchmark sweeping test 2021-06-21 17:40:53 -06:00
tangxifan 07dcf3ad27 [HDL] Add more micro benchmarks for counter, and-gate and mac unit 2021-06-21 16:48:35 -06:00
tangxifan f9e66e1bae [Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name; 2021-06-21 15:27:12 -06:00
tangxifan fce84e564d [Script] Patch on missing string to show in error message 2021-06-18 11:20:35 -06:00
tangxifan 0e01177cf0 [Script] Now openfpga flow script output detailed error message when task is not found 2021-06-18 11:01:45 -06:00
tangxifan 96cb3081ab
Update fix_device_route_chan_width_example_script.openfpga 2021-06-18 09:51:16 -06:00
Andrew Pond 3cfc42cdf9 added testbench CI 2021-06-15 14:16:31 -06:00
tangxifan d40cf98c48 [Test] Update test cases by using default net type in testbench generator 2021-06-14 11:47:28 -06:00
tangxifan eed30605d7 [Test] patch test case 2021-06-09 15:20:55 -06:00
tangxifan d545069aac [Script] Bug fix 2021-06-09 14:50:37 -06:00
tangxifan 52c0ed571b [Test] Patch test case to use proper template 2021-06-09 14:27:02 -06:00
tangxifan c62666e7c3 [Test] Use proper template for some failing tests 2021-06-09 14:24:34 -06:00
tangxifan 4e3f589810 [Script] Patch openfpga shell script to use the new option '--support_icarus_simulator' for 'write_preconfigured_testbench' 2021-06-09 13:53:28 -06:00
tangxifan f9404dc97d [Script] Patch openfpga shell script due to missing a mandatory option in 'write_full_testbench' 2021-06-09 11:55:25 -06:00
tangxifan 9adf94bfd3 [Script] Update all the openshell scripts to deprecate 'write_verilog_testbench' 2021-06-09 11:18:52 -06:00
tangxifan be26c06673 [Script] Update an example script to use 'write_preconfigured_fabric_wrapper' and 'write_preconfigured_testbench' in place of 'write_verilog_testbench' 2021-06-09 10:41:22 -06:00
tangxifan 462326aaa5 [Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench' 2021-06-07 21:50:00 -06:00
tangxifan 5ecd975ec7 [Test] Bug fix 2021-06-07 19:20:10 -06:00
tangxifan 9556f994b4 [Test] Use 'write_full_testbench' in all the memory bank -related test cases 2021-06-07 17:49:40 -06:00
tangxifan a67196178e [Test] Now use 'write_full_testbench' in configuration frame test cases 2021-06-07 13:58:15 -06:00
tangxifan 27fa15603a [Tool] Patch test case due to changes in the template script 2021-06-04 18:17:47 -06:00
tangxifan e9fa44cc25 [Tool] Add fast configuration to the write bitstream command in example shell script 2021-06-04 16:24:56 -06:00
tangxifan 5f96d440ec [Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration 2021-06-04 11:48:05 -06:00
tangxifan ec203d3a5c [Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases 2021-06-04 11:35:23 -06:00
tangxifan 2068291de0 [Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases 2021-06-04 11:32:49 -06:00
tangxifan aa4e1f5f9a [Test] Update test case which uses write_full_testbench openfpga shell script 2021-06-04 11:29:43 -06:00
tangxifan f5e90c9467 [Script] Update openfpga shell script with fast configuration option 2021-06-04 11:28:10 -06:00
tangxifan ebe30fc070 [Test] Deploy write full testbench to multi-head configuration chain test case 2021-06-03 17:08:33 -06:00
tangxifan 8fc90637e0 [Script] Update write_full_testbench example script to support custom device layout in VPR 2021-06-03 17:08:08 -06:00
tangxifan 1e9f6eb439 [Test] update configuration chain test to use new testbench 2021-06-03 15:53:27 -06:00
tangxifan 51ca62a464 [Script] Add example script for write_full_testbench command 2021-06-03 15:48:59 -06:00
Andrew Pond 12b44e0eca added configuration benchmark files 2021-05-13 10:04:23 -06:00
tangxifan c33ca464dc [Test] Deploy new tests to regression test 2021-05-07 12:06:46 -06:00
tangxifan 2baf3ddd2f [Test] Add test cases for 'report_bitstream_distribution' command 2021-05-07 12:06:24 -06:00
tangxifan 7dc7c1b4f5 [Script] Add example openfpga shell script showing how to use 'report_bitstream_distribution' command 2021-05-07 12:05:47 -06:00
tangxifan f1658cb735 [Test] Deploy blinking to test cases 2021-05-06 15:17:45 -06:00
tangxifan 16fff90607 [Benchmark] Add microbenchmark 1-bit blinking 2021-05-06 15:17:27 -06:00
tangxifan f77b81fe5b [Arch] recover the mem16k arch as it is used in other test cases 2021-04-28 15:05:30 -06:00
tangxifan bc34efe337 [Arch] Bug fix in the architecture using BRAM spanning two columns 2021-04-28 14:32:17 -06:00
tangxifan a5e40fbb21
Merge branch 'master' into micro_benchmarks 2021-04-28 14:27:58 -06:00
tangxifan 870432e7f1 [Test] Patch regression test script due to the change of DPRAM test case 2021-04-28 12:45:52 -06:00
tangxifan b72d4bd807 [Test] Update test case for 1kbit DPRAM architectures 2021-04-28 11:28:53 -06:00
tangxifan 117cea295d [Arch] Patch architecture to be compatible with pin names of DPRAM cell 2021-04-28 11:28:23 -06:00
tangxifan a571b063b6 [Benchmark] Add 1k DPRAM benchmark which can fit new arch 2021-04-28 11:26:31 -06:00
tangxifan c24edbd674 [Script] Update yosys script due to arch changes in DPRAM sizes 2021-04-28 10:55:59 -06:00
tangxifan ec4b60f3cc [Arch] Add example arch using 1-kbit DPRAM 2021-04-28 10:47:17 -06:00
tangxifan be98775ae5 [Arch] Reduce the size of DPRAM in example architecture to accelerate testing 2021-04-28 10:45:10 -06:00
tangxifan 5c729657ef [Test] Bug fix in test case for DPRAM whose width = 2 2021-04-28 10:31:22 -06:00
tangxifan 79b27a6329 [Arch] Patch arch using DPRAM block with wide = 2 2021-04-28 10:29:09 -06:00
tangxifan 63309ba72b [HDL] Patch dpram cell 2021-04-27 23:42:31 -06:00
tangxifan 411af10933 [Script] Patch yosys script for 16kbit dual port RAM 2021-04-27 23:41:47 -06:00
tangxifan 834657f2da [Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes 2021-04-27 23:41:14 -06:00
tangxifan 0bec4b3f32 [Test] Update task configuration to use proper openfpgashell script 2021-04-27 23:34:42 -06:00
tangxifan 7d059f7407 [Benchmark] Bug fix in dual port ram 16k benchmark 2021-04-27 23:33:20 -06:00
tangxifan 3c1c33bf1e [Benchmark] Add a microbenchmark just fit 16k dual port ram 2021-04-27 22:51:43 -06:00
tangxifan 7e2368158e [Benchmark] move benchmarks to microbenchmark category 2021-04-27 22:12:30 -06:00
tangxifan 5a85ec9fa0 [Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised 2021-04-27 22:09:10 -06:00
tangxifan dd46780865 [Script] Update yosys script using BRAMs 2021-04-27 21:44:27 -06:00
tangxifan fdfbdc4613 [Test] Update task configuration files to use dedicated yosys script 2021-04-27 20:05:04 -06:00
tangxifan 2802b0895c [HDL] Add yosys technology library for reworked architecture using 16k-bit DPRAM 2021-04-27 19:55:46 -06:00
tangxifan e67095edd2 [HDL] Add 16k-bit dual port ram verilog 2021-04-27 19:55:16 -06:00
tangxifan 0f8aaae2bc [Arch] Patch architecture using 16kbit dual port RAM 2021-04-27 19:54:34 -06:00
tangxifan 1d498bb296 [Benchmark] Add a scalable micro benchmark fifo 2021-04-27 15:26:52 -06:00
tangxifan 6cb4d7d720 [Test] Add the new test to regressiont test 2021-04-27 14:41:38 -06:00
tangxifan b8ced5377f [Test] Add a test case for i/o mapping writer 2021-04-27 14:41:15 -06:00
tangxifan f9fd444b86 [Script] Add an write I/O mapping example script for openfpga shell 2021-04-27 14:40:26 -06:00
tangxifan 1d5e926d9e [Test] Deploy new test to CI 2021-04-26 16:29:54 -06:00
tangxifan 6291871faf [Test] Added a test for the example architecture with 2x2 DSP blocks 2021-04-26 16:28:43 -06:00
tangxifan 8c007c7c49 [Arch] Add a new example architecture where a DSP block occupies a 2x2 grid 2021-04-26 16:28:10 -06:00
tangxifan 7d4c5e3cd1 [Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block 2021-04-26 12:00:57 -06:00
tangxifan 6e87b8875b [Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block 2021-04-26 11:59:25 -06:00
tangxifan b7da22501c [Test] Deply new test to regression test 2021-04-24 15:55:05 -06:00
tangxifan 5adffad602 [Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!! 2021-04-24 15:49:53 -06:00
tangxifan 80f98328df [Test] Update test settings for architecture with fracturable DSP blocks 2021-04-24 15:16:50 -06:00
tangxifan 8b8096f3a8 [HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block 2021-04-24 14:57:09 -06:00
tangxifan a3a98fa21d [Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition 2021-04-24 14:56:10 -06:00