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OpenFPGA
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1060 Commits

Author SHA1 Message Date
tangxifan ad5cce0ae8 [Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals 2021-10-30 15:11:07 -07:00
tangxifan 8dea7e80e6 [Flow] Update yosys script to not use sdff and dffe 2021-10-30 14:56:54 -07:00
tangxifan 40d11a45d9 [Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade 2021-10-30 14:49:56 -07:00
tangxifan b7ad61227d [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF 2021-10-30 14:47:37 -07:00
tangxifan ec184ef532 [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF 2021-10-30 14:46:12 -07:00
tangxifan 0b770f3330 [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 14:36:43 -07:00
tangxifan 59a622a910 [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 14:34:37 -07:00
tangxifan 978c60e75b [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 13:29:38 -07:00
tangxifan 18bab18032 [Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release 2021-10-30 13:20:58 -07:00
tangxifan 16de60e943 [Test] Turn off ACE2 run in bitstream generation only flows 2021-10-30 12:31:14 -07:00
tangxifan 94328351be [Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts 2021-10-30 12:00:06 -07:00
tangxifan 0a449cc24c [HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected 2021-10-30 11:45:01 -07:00
tangxifan 9c06041ce4 [Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff` 2021-10-30 11:27:40 -07:00
Aram Kostanyan 2eef21a1af Fixed port names for mult_36x36 2021-10-26 19:14:43 +05:00
Christophe Alexandre c42acec81e Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py 2021-10-18 10:45:35 +00:00
Christophe Alexandre c3dd704bf3 Fixing typo in run_fpga_flow.py 2021-10-18 09:13:42 +00:00
Christophe Alexandre d411967159 Fixing small typo in run_fpga_flow.py 2021-10-15 10:01:12 +00:00
slt b867db815f
Update fpgaflow_default_tool_path.conf 
Update regex for VPR
 2021-09-17 14:02:26 +08:00
Will c31c1d8b04 Accept absolute project paths as inputs to the 'run_fpga_task.py' script. 2021-08-13 11:08:09 -04:00
tangxifan 9f03ecb160 [Test] Patch test case due to the changes in counter benchmarks 2021-07-02 17:57:39 -06:00
tangxifan 64dcdaec61 [Test] Update all the tasks that use counter benchmark 2021-07-02 17:29:13 -06:00
tangxifan 5a6874e9f1 [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks 2021-07-02 17:28:17 -06:00
tangxifan 8baf60603a [Script] Patching the run_fpga_task.py on pin constraint files 2021-07-02 15:59:29 -06:00
tangxifan fdf94cba83 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 15:28:34 -06:00
tangxifan 3cbe266c44 [Test] Bug fix on the test case for multi-mode FF and pin constraints 2021-07-02 15:27:27 -06:00
Ganesh Gore c67807868c [bugFix] Benchamrk variable declaration 2021-07-02 15:26:39 -06:00
tangxifan 3aacce2a96 Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 14:04:42 -06:00
Ganesh Gore edd5be2cae [CI] Added testcase for benchmark variable 2021-07-02 12:51:34 -06:00
tangxifan dcb89cb16b [Arch] Patch architecture due to missing mode bit definition 2021-07-02 11:41:29 -06:00
tangxifan 5286f9ba25 [Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking 2021-07-02 11:39:00 -06:00
tangxifan 02fd2a69b3 [Script] Add dff with active-low async reset to default yosys tech lib 2021-07-02 11:17:43 -06:00
tangxifan 477e535344 [HDL] Added a multi-mode FF design with configurable asynchronous reset 2021-07-02 11:13:03 -06:00
tangxifan fd85f956c9 [Arch] Update k4n4 arch with true multi-mode flip-flop 2021-07-02 11:08:39 -06:00
tangxifan 0b6a9b06f5 [Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality 2021-07-02 10:39:07 -06:00
Ganesh Gore 1de1f2f2e2 [FLOW] Variable in capital case 2021-07-01 22:26:00 -06:00
Ganesh Gore 81f9dff9ff [Flow] Allows benchmark specific var declaraton 2021-07-01 22:19:53 -06:00
ANDREW HARRIS POND 1d281765ea fixed tab spacing 2021-07-01 16:42:04 -06:00
ANDREW HARRIS POND 808821bb8c fixed errors 2021-07-01 16:40:03 -06:00
ANDREW HARRIS POND 006b54c4bc ready for merge 2021-07-01 15:35:39 -06:00
ANDREW HARRIS POND 8513b8a4ff Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench 2021-07-01 15:29:39 -06:00
ANDREW HARRIS POND 2567fbee05 ready to merge 2021-07-01 15:28:59 -06:00
tangxifan 04ceeefb0a
Merge branch 'master' into verilog_testbench 2021-07-01 14:43:26 -06:00
ANDREW HARRIS POND db9231c225 tests failing with initial blocks 2021-07-01 13:52:28 -06:00
Andrew Pond fab2b069f0 added signal gen regression test to shell script 2021-06-30 16:18:09 -06:00
tangxifan a898537474 [Benchmark] Remove redundant post-synthesis netlist for ``adder_8`` 2021-06-30 15:29:13 -06:00
tangxifan 83d177b13b [Test] Deploy the newly added adder benchmarks to tests 2021-06-30 15:14:24 -06:00
tangxifan 4d4577bb83 [Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders 2021-06-30 15:13:47 -06:00
tangxifan 9eeec05a1f [Test] Bug fix 2021-06-29 19:55:07 -06:00
tangxifan f32ffb6d61 [Test] Bug fix 2021-06-29 18:51:28 -06:00
tangxifan 56b0428eba [Misc] Bug fix 2021-06-29 18:48:19 -06:00