tangxifan
|
4cc8b08a6c
|
[Tool] Add openfpga version display
|
2021-01-23 16:38:00 -07:00 |
|
tangxifan
|
d2defebee9
|
[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
|
2021-01-22 16:42:13 -07:00 |
|
tangxifan
|
3f80a26172
|
[Tool] Bug fix for combinational benchmarks in pre-config testbench generation
|
2021-01-19 18:22:50 -07:00 |
|
tangxifan
|
75b99b78e9
|
[Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks
|
2021-01-19 17:38:51 -07:00 |
|
tangxifan
|
da200658c1
|
[Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks
|
2021-01-19 17:29:59 -07:00 |
|
tangxifan
|
0670c2de59
|
[Tool] Deploy pin constraints to preconfig Verilog module generation
|
2021-01-19 16:56:30 -07:00 |
|
tangxifan
|
8c311b8282
|
[Tool] Bug fix in repacker for considering design constraints
|
2021-01-17 12:26:14 -07:00 |
|
tangxifan
|
2efe513122
|
[Tool] Now repack consider design constraints; test pending
|
2021-01-16 21:57:17 -07:00 |
|
tangxifan
|
bb8e7e25c2
|
[Tool] Start deploying design constraints in repack engine
|
2021-01-16 21:27:12 -07:00 |
|
tangxifan
|
fa67517349
|
[Tool] Add repack design constraints to openfpga command 'repack'
|
2021-01-16 18:49:34 -07:00 |
|
tangxifan
|
ad7a54db1b
|
[Tool] Add repack dc library to compilation
|
2021-01-16 17:20:59 -07:00 |
|
tangxifan
|
87b2c1f3b8
|
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
|
2021-01-15 12:01:53 -07:00 |
|
tangxifan
|
852f5bb72e
|
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
|
2021-01-14 15:38:24 -07:00 |
|
tangxifan
|
9cc9e45b4b
|
[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
|
2021-01-13 15:13:19 -07:00 |
|
tangxifan
|
c0da6b900a
|
[Tool] Bug fix in creating multi-bit clock port connections
|
2021-01-12 18:38:00 -07:00 |
|
tangxifan
|
65b2fe3ab7
|
[Tool] Bug fix in the global tile connection by considering all the subtiles
|
2021-01-10 11:52:38 -07:00 |
|
tangxifan
|
9a441fa5cc
|
[Tool] Upgrade openfpga to support extended global tile port definition
|
2021-01-09 18:47:12 -07:00 |
|
tangxifan
|
cde26597ed
|
[Tool] Bug fix in scan chain builder calling
|
2021-01-04 18:45:47 -07:00 |
|
tangxifan
|
804b721a19
|
[Tool] Bug fix in the configuration chain connection builder
|
2021-01-04 17:41:29 -07:00 |
|
tangxifan
|
bfd305b5a5
|
[Tool] Patch the bug in finding data output ports for CCFF
|
2021-01-04 17:22:30 -07:00 |
|
tangxifan
|
cc91a0aebd
|
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
|
2021-01-04 17:14:26 -07:00 |
|
tangxifan
|
d11a3d9fef
|
[Tool] Avoid outputting signal initialization codes because they are bulky
|
2020-12-06 14:29:16 -07:00 |
|
tangxifan
|
cb2bd2e31c
|
[Tool] Remove register ports for mini local encoders (1-bit data out)
|
2020-12-06 14:21:54 -07:00 |
|
tangxifan
|
6bdfcb0147
|
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
|
2020-12-05 12:44:09 -07:00 |
|
tangxifan
|
6f18688f0e
|
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
|
2020-12-05 10:53:01 -07:00 |
|
tangxifan
|
0da92ad888
|
[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
|
2020-12-04 22:16:51 -07:00 |
|
tangxifan
|
5be9e9b736
|
[Tool] Adapted tools to support I/O in center grid
|
2020-12-04 18:50:13 -07:00 |
|
tangxifan
|
73aaa261d8
|
[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
|
2020-12-04 17:55:25 -07:00 |
|
tangxifan
|
4aa6264b1c
|
[Tool] Rework simulation time period to be sync with actual stimuli
|
2020-12-02 22:58:13 -07:00 |
|
tangxifan
|
b661c39b04
|
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
|
2020-12-02 19:36:36 -07:00 |
|
tangxifan
|
3a708cff21
|
[Tool] Bug fix to enable nature fracturable LUT design
|
2020-11-25 23:01:18 -07:00 |
|
tangxifan
|
c82f01b3ab
|
[Tool] Use conditional operator in signal initialization to eliminate all the warning messages
|
2020-11-23 15:50:23 -07:00 |
|
tangxifan
|
e644545f21
|
[Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors
|
2020-11-23 15:02:06 -07:00 |
|
tangxifan
|
3b2a4c5387
|
[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
|
2020-11-22 20:25:03 -07:00 |
|
tangxifan
|
57a24570f5
|
[Tool] Move icarus and signal initialization options to testbench generator
|
2020-11-22 16:01:31 -07:00 |
|
tangxifan
|
3f91b8433e
|
[Tool] Change the i/o numbering to the clockwise sequence
|
2020-11-13 15:00:25 -07:00 |
|
tangxifan
|
088198c861
|
[Tool] enhance error checking in fabric key parser
|
2020-11-13 10:56:00 -07:00 |
|
tangxifan
|
372fb261fd
|
[Tool] Extend the support on global tile port for I/O tiles
|
2020-11-11 15:09:40 -07:00 |
|
tangxifan
|
e627b6dd5d
|
[Tool] Enhance port attribute checks in tile annotation data structure
|
2020-11-11 13:41:05 -07:00 |
|
tangxifan
|
9cbc374b33
|
[Tool] Add check codes for tile annotation
|
2020-11-11 12:03:13 -07:00 |
|
tangxifan
|
81e56d45d6
|
[Tool] Update FPGA-SDC to use the new data structure for global ports
|
2020-11-10 21:17:17 -07:00 |
|
tangxifan
|
c61ec5a8b8
|
[Tool] Bug fix for defining global ports from tiles
|
2020-11-10 20:31:14 -07:00 |
|
tangxifan
|
dcb50e4f19
|
[Tool] Use use standard data structure to store global port information
|
2020-11-10 19:07:28 -07:00 |
|
tangxifan
|
cbb1545ee3
|
[Tool] Add connection builder for tile global ports to top-level module
|
2020-11-10 16:59:00 -07:00 |
|
tangxifan
|
5fe9c27600
|
[Tool] Remove redundant assertation
|
2020-11-09 09:42:39 -07:00 |
|
tangxifan
|
ba0120bd76
|
[Tool] Remove the limitation on requiring Qb ports for CCFF
|
2020-11-06 11:10:04 -07:00 |
|
tangxifan
|
9b0617ffe6
|
[Tool] Bug fix for mappable I/O support
|
2020-11-04 20:45:51 -07:00 |
|
tangxifan
|
37c10f0cb5
|
[Tool] Add mappable I/O support and enhance I/O support
|
2020-11-04 20:21:49 -07:00 |
|
tangxifan
|
4a2874b2bc
|
[Tool] Refactor the codes for walking through io blocks
|
2020-11-03 13:21:50 -07:00 |
|
tangxifan
|
1e47203c7c
|
[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization
|
2020-11-02 18:35:26 -07:00 |
|
tangxifan
|
e4d974c5c8
|
[Tool] Split io location mapping builder from fabric builder
|
2020-11-02 18:27:34 -07:00 |
|
tangxifan
|
1fd899ecee
|
[Tool] Relex logic block checking codes to skip zero-capacity nodes
|
2020-11-02 16:57:19 -07:00 |
|
tangxifan
|
6b25cf720d
|
[Tool] Comment on the memory efficiency on fabric bitstream address storage
|
2020-10-30 22:09:48 -06:00 |
|
tangxifan
|
b78f8bec16
|
[Tool] Bug fixed for multi-region configuration frame
|
2020-10-30 21:19:20 -06:00 |
|
tangxifan
|
5bcd559851
|
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
|
2020-10-30 17:29:04 -06:00 |
|
tangxifan
|
0d77916041
|
[Tool] Support multi-region frame-based configuration protocol
|
2020-10-30 10:43:11 -06:00 |
|
tangxifan
|
8ef6ae32fb
|
[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
|
2020-10-29 17:35:55 -06:00 |
|
tangxifan
|
987eccf586
|
[Tool] Bug fix in multi-region memory bank; Basic test passed
|
2020-10-29 16:26:45 -06:00 |
|
tangxifan
|
448e88645a
|
[Tool] Support multiple memory banks in top-level module
|
2020-10-29 12:42:03 -06:00 |
|
tangxifan
|
bd49ea95d4
|
[Tool] Add function to comput configuration bits by region
|
2020-10-28 12:37:09 -06:00 |
|
tangxifan
|
446f982410
|
[Tool] Add warning when number of regions defined in fabric key is different than architecture
|
2020-10-28 11:43:05 -06:00 |
|
tangxifan
|
1ef0898f41
|
[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
|
2020-10-12 12:31:51 -06:00 |
|
tangxifan
|
721bcce373
|
[Tool] Change analysis SDC file name to track netlist name
|
2020-10-10 17:43:35 -06:00 |
|
tangxifan
|
e0d7bcfa11
|
[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
|
2020-09-29 12:49:32 -06:00 |
|
tangxifan
|
e988e35f81
|
[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
|
2020-09-29 12:22:10 -06:00 |
|
tangxifan
|
180d72f3e5
|
[Tool] Add regions to fabric bitstream
|
2020-09-28 21:04:08 -06:00 |
|
tangxifan
|
e179a58b15
|
[OpenFPGA Tool] Bug fix for long runtime
|
2020-09-28 20:42:18 -06:00 |
|
tangxifan
|
47f3c79927
|
[OpenFPGA Tool] Bug fix in module manager due to configurable regions
|
2020-09-28 19:08:19 -06:00 |
|
tangxifan
|
f93d46a870
|
[OpenFPGA Tool] Add multiple configuration chain support in top module builder
|
2020-09-28 19:03:19 -06:00 |
|
tangxifan
|
552dddffd0
|
[OpenFPGA Tool] Support configurable regions in module manager
|
2020-09-28 18:13:07 -06:00 |
|
tangxifan
|
052b8b71c7
|
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
|
2020-09-27 20:54:58 -06:00 |
|
tangxifan
|
154f23b108
|
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches
|
2020-09-26 11:54:06 -06:00 |
|
tangxifan
|
1b4e449179
|
[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
|
2020-09-25 21:05:20 -06:00 |
|
tangxifan
|
6bea712db0
|
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
|
2020-09-25 14:54:51 -06:00 |
|
tangxifan
|
8468f25b23
|
[OpenFPGA Tool] Bug fix in the smart fast configuration strategy
|
2020-09-24 16:31:55 -06:00 |
|
tangxifan
|
46b12611a9
|
[OpenFPGA Tool] Bug fix for smart fast configuration
|
2020-09-23 22:04:07 -06:00 |
|
tangxifan
|
154c9045f6
|
[OpoenFPGA Tool] Bug fix for smart fast configuration
|
2020-09-23 21:38:42 -06:00 |
|
tangxifan
|
c2c37d7555
|
[OpenFPGA Tool] Add more print-out for smart fast configuration
|
2020-09-23 21:34:23 -06:00 |
|
tangxifan
|
a3abf81afe
|
[OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration
|
2020-09-23 21:25:06 -06:00 |
|
tangxifan
|
064678fe32
|
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
|
2020-09-23 20:27:52 -06:00 |
|
tangxifan
|
ad881ea4dc
|
[OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank
|
2020-09-23 18:59:25 -06:00 |
|
tangxifan
|
9adeb550dc
|
[OpenFPGA Tool] Bug fix in fabric builder
|
2020-09-23 18:28:00 -06:00 |
|
tangxifan
|
6480b06a2d
|
[OpenFPGA tool] Remove out-of-data test blif, architecture and scripts
|
2020-09-23 11:01:53 -06:00 |
|
tangxifan
|
26f1a5d9ec
|
[OpenFPGA Tool] Bug fix for repacking no local routing architecture
|
2020-09-21 22:22:03 -06:00 |
|
tangxifan
|
c6ac02d210
|
[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation
|
2020-09-20 15:21:33 -06:00 |
|
tangxifan
|
544c44fe46
|
[FPGA-SPICE] Add VDD and VSS port to module definition
|
2020-09-20 14:58:15 -06:00 |
|
tangxifan
|
460fef5807
|
[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
|
2020-09-20 12:58:55 -06:00 |
|
tangxifan
|
222bc86cbf
|
[FPGA-SPICE] Add auxiliary SPICE netlist writer
|
2020-09-20 12:53:28 -06:00 |
|
tangxifan
|
06c0073a3e
|
[FPGA-SPICE] Add SPICE writer for fpga top module
|
2020-09-20 12:43:48 -06:00 |
|
tangxifan
|
1dfb3e06cc
|
[FPGA-SPICE] add SPICE writer for logic blocks
|
2020-09-20 12:38:24 -06:00 |
|
tangxifan
|
5e78e91fdf
|
[FPGA-SPICE] Add SPICE writer for routing blocks
|
2020-09-20 12:27:48 -06:00 |
|
tangxifan
|
0f25b52907
|
[FPGA-Verilog] code format fix
|
2020-09-20 12:18:22 -06:00 |
|
tangxifan
|
2fae311c8e
|
[FPGA-SPICE] Add SPICE writer for memories
|
2020-09-20 12:14:34 -06:00 |
|
tangxifan
|
f284f6f8d0
|
[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
|
2020-09-20 12:03:10 -06:00 |
|
tangxifan
|
6801d260e9
|
[FPGA-SPICE] Add SPICE writer for LUT
|
2020-09-20 11:58:11 -06:00 |
|
tangxifan
|
0f9fce92b2
|
[FPGA-SPICE] Add SPICE writer for routing multiplexers
|
2020-09-20 11:49:02 -06:00 |
|
tangxifan
|
c7e3d97d1b
|
[FPGA-SPICE] Add supply voltage generator
|
2020-09-20 11:19:06 -06:00 |
|
tangxifan
|
15df9b3893
|
[FPGA-SPICE] Add SPICE subcircuit writer
|
2020-09-19 23:01:44 -06:00 |
|
tangxifan
|
82e137cbe4
|
[FPGA-SPICE] Add wire module SPICE writer
|
2020-09-19 19:31:16 -06:00 |
|
tangxifan
|
1b2762386c
|
[FPGA-SPICE] Bug fix for essential gate netlist writing
|
2020-09-19 16:52:30 -06:00 |