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OpenFPGA
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5,388 Commits 70 Branches 8 Tags 105 MiB
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5388 Commits

Author SHA1 Message Date
tangxifan 3d9e913e4e add a benchmark fifo 2018-12-12 16:45:33 -07:00
AurelienUoU cc5a01d476 Fix waveform generation + add benchmark and update go.sh 2018-12-11 22:21:39 -07:00
AurelienUoU a70b0ac9ac Correct go.sh 2018-12-11 15:51:21 -07:00
AurelienUoU 317c3b59c9 Update go.sh and upload pip_add.v 2018-12-11 15:47:05 -07:00
AurelienUoU fb0992bd85 Update go.sh and Makefile 2018-12-11 15:31:32 -07:00
AurelienUoU c2c4e78639 Add pip_add benchmark 2018-12-11 15:29:48 -07:00
AurelienUoU f5ea3ff233 Add an autochecked configuration free testbench 2018-12-11 14:44:13 -07:00
Baudouin Chauviere 79f3db9880 removed the now useless tutorial part 2018-12-10 13:57:01 -07:00
Baudouin Chauviere ba6ace343b Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 2018-12-10 13:48:09 -07:00
LNIS-Projects 55459f7906
Update index.rst 
Reorganization
 2018-12-10 13:46:38 -07:00
LNIS-Projects 56555fc8a0
Update index.rst 
Removed abc from the project because included in Yosys
 2018-12-10 13:46:02 -07:00
tangxifan 8891904e10 Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 2018-12-10 13:30:12 -07:00
tangxifan 72fbd8d6a8 update blif reader to identify clock signals 2018-12-10 13:28:44 -07:00
LNIS-Projects 7bcc61b0f2
Update .gitmodules 
Unused submodule blocking the compilation of the documentation
 2018-12-10 12:07:05 -07:00
Baudouin Chauviere 1472e7aa62 Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 2018-12-10 10:25:25 -07:00
AurelienUoU a69c2e1882 Add security in checking to avoid simulation glitch error 2018-12-10 09:46:16 -07:00
AurelienUoU 7020d9b4b6 Edit waveform generator + fix clock mapping in autochecked testbench 2018-12-09 15:48:59 -07:00
Baudouin Chauviere afbe5bd3ff need abc_with_bb_support for ace compilation 2018-12-09 15:45:09 -07:00
AurelienUoU 5e94b7093d Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench) 2018-12-08 22:57:54 -07:00
Aur??Lien ALACCHI 10866d1852 Correct verilog syntax error in autocheck testbench 2018-12-08 17:40:23 -07:00
Aur??Lien ALACCHI d716b67e23 Correct syntax error in autocheck testbench 2018-12-08 17:29:56 -07:00
Aur??Lien ALACCHI 0580d8243f Add Autochek testbench option 2018-12-08 17:19:12 -07:00
Baudouin Chauviere b0fcbc0960 remove abc with bb support 2018-12-08 16:40:57 -07:00
Baudouin Chauviere 79930982cf Changed for the naming 2018-12-08 16:19:38 -07:00
Baudouin Chauviere 4440066565 added the script to launch vpr with picorv 2018-12-08 16:01:58 -07:00
Baudouin Chauviere c130404158 add a section for picorv generation through the flow 2018-12-08 11:33:14 -07:00
Aur??Lien ALACCHI 4cc875a5a5 fix a bug in wired LUT 2018-12-06 18:00:17 -07:00
tangxifan b3c1018e28 fixed a bug in wired LUT 2018-12-06 16:50:30 -07:00
Aur??Lien ALACCHI 7795d4e7fd Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 
unknown merge
 2018-12-06 15:35:22 -07:00
Aur??Lien ALACCHI eebdf7cb10 Add possibility to choose default value for initialization 2018-12-06 15:34:14 -07:00
Baudouin Chauviere 0b6fcc8875 Added the aliases for Yosys-ABC 2018-12-06 15:06:01 -07:00
Baudouin Chauviere 0b1ccf7722 and in the config path as well 2018-12-06 14:57:32 -07:00
Baudouin Chauviere 6a54592a7b removed abc and added yosys in the flow 2018-12-06 14:55:36 -07:00
Baudouin Chauviere b6bb419e1d add a ModelSim option 2018-12-06 14:13:37 -07:00
Baudouin Chauviere fe47b3d21f Changing arch from memory dec to scff. Get the bitstream from go.sh 2018-12-06 14:03:17 -07:00
BaudouinChauviere 88af64c606
Update eda_flow.rst 
Distributions compilable added
 2018-12-05 16:29:07 -07:00
BaudouinChauviere d0ac931daa
Update README.md 
Small correction
 2018-12-05 16:27:37 -07:00
BaudouinChauviere 576feb600f
Update eda_flow.rst 
Completed with FPGA-Verilog/Bitstream and corrected few errors
 2018-12-05 16:24:03 -07:00
Aur??Lien ALACCHI 8281b7346b Edit auto-generated modelsim script 2018-12-05 16:15:29 -07:00
Aur??Lien ALACCHI 44b7f7f3d4 Correct sub_modules.v generation to include decoders.v when necessary 2018-12-05 13:52:25 -07:00
Aur??Lien ALACCHI dc4accedd9 Add forgottent files + add parameter transmission from verilog_api.c 2018-12-05 11:33:14 -07:00
Aur??Lien ALACCHI 9a8c7b391a Add process for modelsim script autogeneration 2018-12-05 09:20:47 -07:00
Aur??Lien ALACCHI 75d64db0f9 Add verilog header sub_module.v file generation 2018-12-04 18:42:47 -07:00
Aur??Lien ALACCHI 8ac566ecc0 Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
BaudouinChauviere 0f87fb9c3f
Update file_organization.rst 
Correction on the routing
 2018-12-03 14:21:40 -07:00
BaudouinChauviere e541834bd0
Update file_organization.rst 
Made similar to the SPICE one
 2018-12-03 14:20:34 -07:00
BaudouinChauviere cd301a5bb8
Update file_organization.rst 
Correction of the hierarchy
 2018-12-03 14:09:11 -07:00
BaudouinChauviere 9c97125b0d
Update spice_simulation.rst 
typo
 2018-12-03 13:42:45 -07:00
BaudouinChauviere b8f702e16d
Update file_organization.rst 
Creation of the table for better understanding
 2018-12-03 13:40:42 -07:00
BaudouinChauviere 10cbd2efef
Update index.rst 
Commenting the multi mode out until more mature
 2018-12-03 11:50:13 -07:00