637dd08bea
[test] fixed a bug
2024-11-26 18:09:39 -08:00
a1a5f8cfb6
[test] add new test to valid force clock tap mux routing
2024-11-26 17:36:02 -08:00
d71e7f7412
[test] add new test to validate default mode bit overwrite
2024-11-25 16:06:40 -08:00
ca48841ae3
Pass in the OpenFPGA root dir
2024-07-29 11:04:03 -07:00
3e3f089823
Get the filepath using definition under [OpenFPGA_SHELL]
2024-07-28 19:24:48 -07:00
0d9f1a3c6b
Forward searching the config bit + some minor refactor
2024-07-28 19:12:34 -07:00
933155b08f
Update test flow
2024-07-27 23:52:54 -07:00
fbe5ae6bd3
Update test
2024-07-26 02:18:08 -07:00
9641aaf6c4
Update test
2024-07-26 02:17:25 -07:00
2ef362d53d
Init support overwriting bitstream
2024-07-25 17:40:46 -07:00
4d9aacdf8f
[test] add and deploy new benchmark
2024-06-02 14:27:02 -07:00
ad2d101554
[test] deploy new benchmarks
2024-06-02 14:23:08 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
a1169beaf0
Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:34:49 -08:00
7475a002b6
Update repack_design_constraints.xml by changing the separater between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:33:55 -08:00
6055a42196
add test case
2023-12-01 03:04:32 -08:00
c6f33bcd7f
[test] add new tests to cover the new features
2023-10-06 18:41:57 -07:00
7d83fc914c
[core] ad a new test case
2023-10-06 18:31:54 -07:00
efc9bf9907
[test] added new test case to validate bitstream generation
2023-06-19 12:40:37 -07:00
d1e951e52e
[test] debugging
2023-01-24 17:57:34 -08:00
f964c9ed67
[test] debug
2023-01-24 15:48:57 -08:00
8174f53796
[test] deploy new test to fpga bitstream regression
2023-01-24 15:42:01 -08:00
fec84d76d1
[arch] adding tech lib;
2023-01-24 15:22:34 -08:00
d60d0540da
[test] adding a new test case to validate the bitstream overloading for DSP blocks
2023-01-24 14:58:52 -08:00
0565ca7aca
[script] add missing files
2022-09-29 16:14:38 -07:00
ce0fbe1765
[test] fixed a few bugs
2022-09-29 15:32:31 -07:00
9bc9b61d35
[test] fixed a few bugs
2022-09-29 15:11:30 -07:00
f5e7ec4dd1
[test] add a new test case to validate wire lut case
2022-09-29 14:28:59 -07:00
b630d60b7e
[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
2022-09-20 14:14:18 -07:00
c48f750f86
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
2022-09-01 20:10:29 -07:00
9832722056
[test] now add QuickLogic memory bank to fpga bitstream regression tests
2022-05-25 11:42:32 +08:00
86347a9d49
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
2022-05-25 11:19:49 +08:00
758453f725
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-21 02:21:00 +05:00
6a4cc340a3
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00
ff264c00a2
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
2021-10-31 11:51:34 -07:00
c8e9dfbeda
[Test] bug fix
2021-10-30 16:50:57 -07:00
335347a74f
[Test] Bug fix
2021-10-30 15:48:25 -07:00
be47e78289
[Arch] Change arch for Sapone test
2021-10-30 15:23:19 -07:00
ad5cce0ae8
[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
2021-10-30 15:11:07 -07:00
16de60e943
[Test] Turn off ACE2 run in bitstream generation only flows
2021-10-30 12:31:14 -07:00
189ade6c1e
[Test] Bug fix
2021-10-05 19:17:34 -07:00
f74ea5d39a
[Test] Use the new openfpga shell script in don't care bit tests
2021-10-05 19:14:44 -07:00
50604e4589
[Test] move test cases
2021-10-05 19:02:43 -07:00
fed6c133b1
[Test] Add new tests to validate the correctness of bitstream files with don't care bits
2021-10-05 18:59:33 -07:00
2baf3ddd2f
[Test] Add test cases for 'report_bitstream_distribution' command
2021-05-07 12:06:24 -06:00
b8ced5377f
[Test] Add a test case for i/o mapping writer
2021-04-27 14:41:15 -06:00
578d81b67a
[Test] Patch task configuration file
2021-04-19 16:15:00 -06:00
5976cc0a1c
[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
2021-04-19 15:54:18 -06:00
e19fc15fec
[Test] bug fix in test case
2021-02-18 19:37:45 -07:00
2e88b035ed
[Test] Add wire LUT repacker test case
2021-02-18 19:37:44 -07:00
tangxifan
chungshien-chai
chungshien
Yitian4Debug
ubuntu
Aram Kostanyan