riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[test] fixed a bug

This commit is contained in:
tangxifan 2024-11-26 18:09:39 -08:00
parent 296f318745
commit 637dd08bea
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga_flow/tasks/fpga_bitstream/force_clock_tap_routing/config/pin_constraints.xml
View File

@ -1,4 +1,4 @@
<pin_constraints>
<set_io pin="clk[0]" net="OPEN"/>
<set_io pin="clk[0]" net="clk"/>
<set_io pin="clk[1]" net="OPEN"/>
</pin_constraints>

4
openfpga_flow/tasks/fpga_bitstream/force_clock_tap_routing/config/task.conf
View File

@ -31,11 +31,11 @@ openfpga_route_clock_options=
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_top = and2_latch
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=