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OpenFPGA
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4,004 Commits 70 Branches 8 Tags 104 MiB
Commit Graph

715 Commits

Author SHA1 Message Date
tangxifan 2e45a6143b [Engine] Fix a critical bug which causes flatten memory tests failed 2021-09-15 15:11:58 -07:00
tangxifan f2aa31ddb1 [FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank 2021-09-15 13:45:30 -07:00
tangxifan 061952b7fa [Engine] Bug fix in computing local WLs for GRID/CB/SB 2021-09-15 11:51:00 -07:00
tangxifan 26b1e48723 [Engine] Merge BL/WLs in the Grid/CB/SB modules 2021-09-15 11:27:55 -07:00
tangxifan 4af6413c97 [Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column 2021-09-10 17:03:44 -07:00
tangxifan ba1e277dc9 [Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine 2021-09-10 15:05:46 -07:00
tangxifan 35c7b09888 [Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank 2021-09-09 15:23:29 -07:00
tangxifan b787c4e100 [Engine] Register QL memory bank as a legal protocol 2021-09-09 15:06:51 -07:00
tangxifan 1aac3197eb [FPGA-Verilog] Upgrade testbench generator to support QL memory bank 2021-09-05 21:38:00 -07:00
tangxifan 6f09f5f7ad [FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank 2021-09-05 21:25:58 -07:00
tangxifan 1085e468e2 [Engine] Move most utilized functions for memory bank configuration protocol to a separated source file 2021-09-05 20:45:56 -07:00
tangxifan 475ce2c6d9 [Engine] Upgrade fabric generator in support QL memory bank connections 2021-09-05 17:49:01 -07:00
tangxifan ed80d6b3f4 [Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier 2021-09-05 13:23:38 -07:00
tangxifan cf2e479d18 [Engine] Refactor the TopModuleNumConfigBits data structure 2021-09-05 12:01:38 -07:00
tangxifan f75456e304 [Engine] Update BL/WL estimation function for QL memory bank protocol 2021-09-05 11:53:33 -07:00
tangxifan 5759f5f35b [Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder 2021-09-03 17:55:23 -07:00
tangxifan e9d29e27e5 [Tool] Bug fix 2021-07-02 15:32:30 -06:00
tangxifan 6e6c3e9fa4 [Tool] Patch the critical bug in the use of signal polarity in pin constraints 2021-07-02 15:26:21 -06:00
tangxifan 9074bffa68 [Tool] Support customized default value in pin constraint file 2021-07-01 23:43:19 -06:00
tangxifan d0e4f8521f [Tool] Bug fix on the reset stimuli 2021-07-01 19:58:54 -06:00
tangxifan b5df1f9aeb [Tool] Bug fix for redundant endif in netlists 2021-06-29 17:02:16 -06:00
tangxifan b83eef47b4 [Tool] Bug fix for testbench generation without self checking codes 2021-06-29 16:27:29 -06:00
tangxifan 6a260cadbf [Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose 2021-06-29 15:42:23 -06:00
tangxifan 7ac7de789e [Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes 2021-06-29 15:26:40 -06:00
tangxifan 77dddaeb39 [Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions 2021-06-29 14:26:33 -06:00
tangxifan a3208b332b [Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL 2021-06-29 11:50:53 -06:00
tangxifan dfe1db996a [Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time 2021-06-29 09:56:04 -06:00
tangxifan 87446a14c3 [Tool] Bug fix for the option ``--embed_bitstream none`` 2021-06-27 19:45:06 -06:00
tangxifan 991062e9bf [Tool] Bug fix 2021-06-25 15:22:42 -06:00
tangxifan 90163fab6c [Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>' 2021-06-25 15:06:07 -06:00
tangxifan 2bb514c51a [Tool] Support time unit in writing simulation information file 2021-06-25 10:33:29 -06:00
tangxifan bcc16d732c [Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches 2021-06-25 10:10:16 -06:00
tangxifan 67dec810eb [Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes 2021-06-24 17:27:32 -06:00
tangxifan 549657e1fb [Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base 2021-06-24 17:13:36 -06:00
tangxifan 5364d8104f [Tool] Add signal_init option to preconfigured fabric wrapper writer 2021-06-24 17:07:41 -06:00
tangxifan 21d1519658 [Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option 2021-06-24 16:56:28 -06:00
tangxifan ce3c80f499
Merge branch 'master' into dev 2021-06-23 09:15:03 -06:00
tangxifan cbbf601edc [Tool] Fix a compiler warning due to uninitialized data structure 2021-06-18 16:20:13 -06:00
tangxifan fed975c52a [Tool] Add postfix removal support in write_io_mapping command 2021-06-18 16:13:50 -06:00
tangxifan d9d57aad42 [Tool] Added default net type options to verilog testbench generator command 2021-06-14 11:37:49 -06:00
tangxifan 7ade48343c [Tool] Deprecate command 'write_verilog_testbench' 2021-06-09 17:06:01 -06:00
tangxifan 2299ce3157 [Tool] Preconfigured testbench writer now supports icarus simulator 2021-06-09 13:49:25 -06:00
tangxifan 3bc8e760db [Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command 2021-06-09 11:14:45 -06:00
tangxifan 89fb672631 [Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use 2021-06-09 10:49:00 -06:00
tangxifan 97396eda2b [Tool] Add a new command 'write_simulation_task_info' 2021-06-08 22:10:02 -06:00
tangxifan d2275b971d [Tool] Add a new command 'write_preconfigured_testbench' 2021-06-08 21:53:51 -06:00
tangxifan 85679c0fe2 [Tool] Bug fix in the top testbench switch due to fast configuration 2021-06-08 21:32:26 -06:00
tangxifan 8db19c7af9 [Tool] Add a new command 'write_preconfigured_fabric_wrapper' 2021-06-08 21:28:16 -06:00
tangxifan 5075c68418 [Tool] Remove duplicated codes on fast configuration 2021-06-08 20:58:04 -06:00
tangxifan 4aef9d5c96 [Tool] Remove redundant codes 2021-06-07 21:54:01 -06:00