Commit Graph

198 Commits

Author SHA1 Message Date
Xifan Tang ac378febef update doc about time units in SDC generator 2020-06-11 19:31:03 -06:00
Xifan Tang d18e924a89 Update documentation on new fpga_sdc option 2020-06-11 19:31:03 -06:00
Xifan Tang ecdbdcb592 update documentation on new SDC options 2020-06-11 19:31:02 -06:00
Xifan Tang 52adebacfb update doc for file options in openfpga bitstream 2020-04-21 14:40:53 -06:00
Xifan Tang b4542ea34b minor fix on doc about the global and general purpose port 2020-04-09 17:10:04 -06:00
Xifan Tang d99776b260 update documentation on the global I/O ports 2020-04-08 18:18:53 -06:00
Xifan Tang b9ade3fcb6 documentation update to introduce new features in script mode of OpenFPGA shell 2020-04-08 14:13:28 -06:00
Xifan Tang 55e68896d6 doc update for the support on std cell MUX2 and examples 2020-04-07 12:01:13 -06:00
Xifan Tang 7a4137fdcf doc update for packable XML syntax in VPR 2020-04-06 18:37:05 -06:00
Xifan Tang 1a3a748dd2 update documentation with the support on spypads and global I/O ports 2020-04-05 20:12:28 -06:00
Xifan Tang 6ce0fe4ef2 doc update for FPGA-bitstream to better motivate the different types of bitstream 2020-04-01 12:57:28 -06:00
Xifan Tang fd8248d9dd update documentation: the addon syntax on VPR and configuration protocols 2020-04-01 12:35:52 -06:00
tangxifan 78964ce71c update documentation on the through channel 2020-03-27 11:34:39 -06:00
Xifan Tang b4221e94bb add documentation on the tileable routing and thru channel support 2020-03-25 16:52:42 -06:00
Xifan Tang cb6afea07c update documentation on a new option in FPGA-SDC to constrain zero-delay paths 2020-03-25 16:00:25 -06:00
Xifan Tang 3a74fb7a04 update documentation for the new options 2020-03-25 15:23:21 -06:00
Xifan Tang 7e3a8e5794 typo fixed in fpga-bitstream documentation 2020-03-22 16:27:12 -06:00
Xifan Tang 75dfe6a045 update documentation for write_gsb_to_xml functionality 2020-03-22 16:21:35 -06:00
tangxifan 1d766d2a70 minor format fix on documentation 2020-03-11 10:22:30 -06:00
Xifan Tang b941ac8a4a remove deprecated options 2020-03-10 20:58:00 -06:00
Xifan Tang 8037d1ad93 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-03-10 20:55:02 -06:00
Xifan Tang 9f743f7f4e add openfpga shell documentation 2020-03-10 20:54:42 -06:00
tangxifan 0da6f00af5 start reworking the openfpga tool documentation 2020-03-10 17:29:35 -06:00
tangxifan 089cc5e86e update documentation on circuit model annotation on VPR architecture 2020-03-10 16:51:50 -06:00
tangxifan 7195564455 reworked circuit model examples in documentation. Now we are consistent to latest syntax 2020-03-10 16:17:20 -06:00
tangxifan 54dfdc0cc1 update general documentation on circuit library 2020-03-10 12:18:12 -06:00
tangxifan 2a3c5b98a5 minor format fix in documentation 2020-03-09 21:25:13 -06:00
Xifan Tang d14fa16905 finish documentation update on technology library 2020-03-09 21:17:25 -06:00
Xifan Tang cb7e4a1dfa finish documentation the simulation settings in VPR8 integration 2020-03-09 20:03:37 -06:00
tangxifan 751735bf41 update documentation in simulation setting syntax 2020-03-09 17:40:33 -06:00
tangxifan 3c7fd30e12 merged tutorial to online documentation and reworked compilation guidelines 2020-03-09 13:58:24 -06:00
tangxifan af6319a6b0 reworked motivation in documentation 2020-03-09 11:27:25 -06:00
tangxifan 73da4a1d6e rework motivation for FPGA-Verilog and FPGA-Bitstream in documentation 2020-03-09 10:32:03 -06:00
tangxifan f821e60405 clean up deadlinks in doc 2020-03-09 10:15:16 -06:00
tangxifan d61ae5561b start cleanup the documentation for openfpga shell 2020-03-09 09:44:19 -06:00
tangxifan f67981afa8 update ducoumentation to explain lib_name XML syntax 2020-01-08 14:22:17 -07:00
tangxifan 13f964ea72 add bitstream file format introduction 2019-12-04 13:41:31 -07:00
tangxifan 40bddd4ed7 add FPL'19 paper to documentation reference 2019-12-04 12:05:30 -07:00
tangxifan 323c4fdc9a clean up documentation build warnings and add guidelines for port naming 2019-12-04 11:59:10 -07:00
AurelienUoU 36f7624b95 Point to point truth table typo fix 2019-10-01 13:07:27 -06:00
AurelienUoU e2867019e1 Typo fixing 2019-09-30 10:38:02 -06:00
AurelienUoU 74f7a3cfb2 Doc fixing 2019-09-30 10:29:42 -06:00
AurelienUoU 5ac79f4805 Point to point documentation 2019-09-30 10:00:46 -06:00
Ganesh Gore 48ec1eefcd Added fpga_task cmd options in doc [ci skip] 2019-09-02 02:45:05 -06:00
Ganesh Gore 241b001282 Added openfpga_task doc 2019-09-01 22:15:53 -06:00
Ganesh Gore 32d47d6b8b Update document + Travis cache check 2019-08-31 16:13:47 -06:00
Ganesh Gore 06c0dbb328 Added docuementation for fpga_flow 2019-08-31 15:19:34 -06:00
Ganesh Gore 937ebd1b85 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-08-25 00:53:18 -06:00
Ganesh Gore c4180fad6d Added .gitignore to build docs locally 2019-08-25 00:49:04 -06:00
tangxifan 42b528be57 doc updates 2019-08-21 15:11:25 -06:00
tangxifan 9c43b1b753 complete refacotriing the inv and buf part in submodules 2019-08-21 14:54:05 -06:00
tangxifan b207050b03 minor fix in documentation 2019-08-06 14:17:57 -06:00
tangxifan fc93a4941a update documentation 2019-08-06 14:17:56 -06:00
tangxifan 7603850d72 complete documentation for new features 2019-08-06 14:17:56 -06:00
tangxifan 8a046394f8 add documentation for multi-mode configurable block support 2019-07-30 16:47:41 -06:00
Xifan Tang afd78604c9 Merge branch 'dev' into documentation: resolved conflicts and add logo files 2019-07-17 17:50:11 -04:00
Xifan Tang e7b40f06b0 Add documentation for fracturable LUTs 2019-07-17 15:21:07 -04:00
AurelienUoU 1cf4e78502 Update documentation and help 2019-07-15 21:16:15 -06:00
AurelienUoU df53f6da2c Updates FPGA-Verilog command lines 2019-07-05 13:41:34 -06:00
AurelienUoU 9e99048815 Update documentation
Merge branch 'heterogeneous' of https://github.com/LNIS-Projects/OpenFPGA into heterogeneous
2019-07-05 11:56:02 -06:00
AurelienUoU 27dbc527a0 Update Readme 2019-07-05 11:06:55 -06:00
AurelienUoU f56adc6815 Update documentation 2019-07-05 10:20:16 -06:00
BaudouinChauviere cb34ac0243
Update sc_flow.rst 2019-04-01 16:30:31 -06:00
BaudouinChauviere 361bbc13e3
Update func_verify.rst 2019-04-01 16:29:42 -06:00
BaudouinChauviere a176bf3a19
Update file_organization.rst 2019-04-01 16:28:48 -06:00
BaudouinChauviere 01371ce54d
Update customize_subckt.rst 2019-04-01 16:27:06 -06:00
BaudouinChauviere 1ea7ec3265
Update spice_simulation.rst 2019-04-01 16:26:02 -06:00
BaudouinChauviere cfdc072164
Update file_organization.rst 2019-04-01 16:25:09 -06:00
BaudouinChauviere fcc3bf0967
Update command_line_usage.rst 2019-04-01 16:23:24 -06:00
BaudouinChauviere f4b72bd4e1
Update link_circuit_modules.rst 2019-04-01 16:21:59 -06:00
BaudouinChauviere ce300c196c
Update circuit_modules.rst 2019-04-01 16:13:23 -06:00
BaudouinChauviere 6e065ef3b3
Update tech_lib.rst 2019-04-01 16:09:31 -06:00
BaudouinChauviere aed779ca3d
Update spice_sim_setting.rst 2019-04-01 16:08:00 -06:00
BaudouinChauviere 4900caaed9
Update generality.rst 2019-04-01 16:04:17 -06:00
BaudouinChauviere 33df25366c
Update eda_flow.rst
Correction fix
2019-04-01 16:02:47 -06:00
BaudouinChauviere d6261f1f59
Update motivation.rst
Typo and better explanations correction
2019-04-01 15:57:04 -06:00
Baudouin Chauviere 39f7b0b9a2 Update of the doc for better fit with the current version 2019-04-01 11:55:28 -06:00
BaudouinChauviere 5dbcfa6d70
Repair broken link 2019-01-03 18:26:30 +01:00
BaudouinChauviere 28010f6c91
Testing another link method 2019-01-03 18:24:06 +01:00
Laboratory for Nano Integrated Systems (LNIS) 30f2ada557
Repaired broken links 2019-01-03 18:18:03 +01:00
LNIS-Projects 77dd7f3e04
correction of the name of the figure 2018-12-29 01:45:45 +01:00
LNIS-Projects 0f6ac32f43
Further resizing 2018-12-29 01:44:24 +01:00
LNIS-Projects 38a3b01520
Resize the images 2018-12-29 01:42:43 +01:00
Baudouin Chauviere 9ee50de26a Adding information on the layout 2018-12-29 01:14:26 +01:00
Baudouin Chauviere 0a5391c14f Addition of some illustrations 2018-12-26 18:16:16 +01:00
LNIS-Projects de7d646fa0
Update func_verify.rst
Functional Verification documentation
2018-12-26 18:05:24 +01:00
LNIS-Projects c0626e9a1c
Adding the Verification Step from ModelSim 2018-12-26 18:00:03 +01:00
LNIS-Projects c506e16d33
Update command_line_usage.rst
Small fix
2018-12-22 14:46:15 +01:00
LNIS-Projects ba303450e2
Update file_organization.rst 2018-12-22 14:45:00 +01:00
LNIS-Projects 5fa6c84087
New fpga_verilog commands documented 2018-12-22 14:39:51 +01:00
LNIS-Projects 55459f7906
Update index.rst
Reorganization
2018-12-10 13:46:38 -07:00
LNIS-Projects 56555fc8a0
Update index.rst
Removed abc from the project because included in Yosys
2018-12-10 13:46:02 -07:00
BaudouinChauviere 88af64c606
Update eda_flow.rst
Distributions compilable added
2018-12-05 16:29:07 -07:00
BaudouinChauviere 576feb600f
Update eda_flow.rst
Completed with FPGA-Verilog/Bitstream and corrected few errors
2018-12-05 16:24:03 -07:00
BaudouinChauviere 0f87fb9c3f
Update file_organization.rst
Correction on the routing
2018-12-03 14:21:40 -07:00
BaudouinChauviere e541834bd0
Update file_organization.rst
Made similar to the SPICE one
2018-12-03 14:20:34 -07:00
BaudouinChauviere cd301a5bb8
Update file_organization.rst
Correction of the hierarchy
2018-12-03 14:09:11 -07:00
BaudouinChauviere 9c97125b0d
Update spice_simulation.rst
typo
2018-12-03 13:42:45 -07:00
BaudouinChauviere b8f702e16d
Update file_organization.rst
Creation of the table for better understanding
2018-12-03 13:40:42 -07:00
BaudouinChauviere 10cbd2efef
Update index.rst
Commenting the multi mode out until more mature
2018-12-03 11:50:13 -07:00