tangxifan
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4b3142c4ee
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[Architecture File] Patch openfpga architecture with default circuit model definition
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2020-08-23 15:13:28 -06:00 |
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tangxifan
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9101ba1021
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[Architecture Language] Update openfpga architecture files for default models
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2020-08-23 14:55:44 -06:00 |
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tangxifan
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ac8e937a50
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[Documentation] Update for default circuit model rules
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2020-08-23 14:08:38 -06:00 |
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tangxifan
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9c66a35bf6
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[arch language] Now circuit library will automatically identify the default circuit model if needed
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2020-08-23 14:06:03 -06:00 |
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tangxifan
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b83319bf14
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[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
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2020-08-23 13:48:22 -06:00 |
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tangxifan
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fb5a5a2448
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[documentation] remove the limitation on through channels
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2020-08-19 20:12:49 -06:00 |
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tangxifan
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6c925dcded
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[regression test] Add more tests for thru channels and deploy to CI
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2020-08-19 20:11:37 -06:00 |
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tangxifan
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1a3e020174
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deploy through channel test case to CI
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2020-08-19 20:04:01 -06:00 |
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tangxifan
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8041c90f12
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bug fix in through channel support in tileable routing
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2020-08-19 20:01:50 -06:00 |
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tangxifan
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881672d46a
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update thru channel arch for avoid buggy pin locations
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2020-08-19 19:52:35 -06:00 |
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tangxifan
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47f15729ad
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update doc about the limitation on using tileable routing
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2020-08-19 18:37:28 -06:00 |
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tangxifan
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d6d17675e2
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update docoumentation about the constraints when using tileable rr_graph generator
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2020-08-19 18:01:32 -06:00 |
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tangxifan
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bf08e1841c
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add new test case using thru channels
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2020-08-19 17:58:34 -06:00 |
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tangxifan
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f3ca1c0973
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fix rr_graph on thru routing channel support
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2020-08-19 17:28:25 -06:00 |
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tangxifan
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f0bc6f83f1
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disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks
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2020-08-19 15:34:59 -06:00 |
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tangxifan
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18735894f9
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bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
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2020-08-19 15:27:30 -06:00 |
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tangxifan
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3273f441fe
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bug fix in the flagship vpr arch
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2020-08-19 15:23:20 -06:00 |
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tangxifan
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aa4a9b28cc
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start testing the initial offset in the flagship architecture
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2020-08-19 15:03:46 -06:00 |
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tangxifan
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161d660837
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update documentation for the initial offset when mapping physical pins
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2020-08-19 15:00:46 -06:00 |
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tangxifan
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3eea12ceae
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added a new XML syntax: initial offset for physical mode pin mapping
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2020-08-19 14:43:44 -06:00 |
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tangxifan
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f631245b2b
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bug fix and enriched debugging info print out
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2020-08-19 13:41:04 -06:00 |
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tangxifan
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79b6ff3cb0
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relax checking for device annotation as we support multi-port during physical mode pin mapping
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2020-08-19 12:44:51 -06:00 |
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tangxifan
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f64079641d
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bug fix in flagship vpr arch with frac mem and dsp
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2020-08-19 12:43:58 -06:00 |
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tangxifan
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af1c7c6f29
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start fixing the bug in thru channels
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2020-08-19 12:18:35 -06:00 |
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tangxifan
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d7efdf35b6
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add custom pin location to the flagship vpr arch with frac mem and dsp
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2020-08-19 11:15:25 -06:00 |
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tangxifan
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dbd93e429d
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now pro_blif.pl can accept customized clock name
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2020-08-19 09:43:44 -06:00 |
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tangxifan
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743167521a
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add Verilog design for fracturable 32k memory
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2020-08-18 21:13:46 -06:00 |
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tangxifan
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42b5ea2cb1
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bug fix in openfpga arch for frac mem and dsp
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2020-08-18 20:42:36 -06:00 |
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tangxifan
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3ee4e10aa8
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bug fix in the frac mem & DSP vpr arch
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2020-08-18 17:25:45 -06:00 |
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tangxifan
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098859fe06
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bug fix in the frac memory & DSP architecture
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2020-08-18 15:05:51 -06:00 |
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tangxifan
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21c7eaa9cf
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add 36-bit fracturable multiplier Verilog
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2020-08-18 14:06:08 -06:00 |
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tangxifan
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53f87f44b4
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update documentation for the multi-port support in physical pb_pin
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2020-08-18 12:44:38 -06:00 |
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tangxifan
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2712c354a9
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now physical pb_port binding support multiple ports
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2020-08-18 12:38:56 -06:00 |
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tangxifan
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f833e0ec66
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add a flagship architecture using fracturable memory and dsp
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2020-08-17 17:49:51 -06:00 |
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tangxifan
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cfd035bf8f
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update tutorials about the verilog-to-verification
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2020-08-17 14:33:51 -06:00 |
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tangxifan
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1ca2829868
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update readme for vpr architecture naming
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2020-08-17 13:54:26 -06:00 |
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tangxifan
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cadf29022e
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add README to explain the organization of regression tests
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2020-07-28 13:44:06 -06:00 |
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tangxifan
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1e53d79c57
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deploy large bitstream regression tests to CI
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2020-07-28 12:41:58 -06:00 |
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tangxifan
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f33422d4d7
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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tangxifan
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534c609e17
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add fixed layouts to a flagship architecture to test bitstream generation runtime
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2020-07-28 11:51:50 -06:00 |
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tangxifan
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a156807559
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enrich basic regression tests to cover more critical microbenchmarks
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2020-07-27 19:47:43 -06:00 |
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tangxifan
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9809db01c5
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deploy load_arch_bitstream test case to CI
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2020-07-27 19:39:14 -06:00 |
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tangxifan
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5d83abb2cf
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bug fix in read architecture bitstream and regression tests
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2020-07-27 19:37:05 -06:00 |
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tangxifan
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9a7364c6e6
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bug fix in fabric bitstream XML syntax
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2020-07-27 19:22:36 -06:00 |
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tangxifan
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31e7a753a6
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-07-27 19:22:16 -06:00 |
ganeshgore
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747c062f86
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BugFix : Flow script accepts extra OpenFPGA arguments
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2020-07-27 18:10:43 -06:00 |
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tangxifan
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50cc4dfba3
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classify regression test to dedicated categories
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2020-07-27 17:18:59 -06:00 |
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tangxifan
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9add82148f
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refactored CI for split regression tests in terms of OpenFPGA tools
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2020-07-27 17:05:46 -06:00 |
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tangxifan
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5595ee9052
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refine the test case for load external arch bitstream
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2020-07-27 16:53:29 -06:00 |
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tangxifan
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f773491f87
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update documentation to sync with the new fabric bitstream format
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2020-07-27 16:37:10 -06:00 |