refactored CI for split regression tests in terms of OpenFPGA tools

.travis.yml

@@ -96,7 +96,25 @@ jobs:
       name: "FPGA-Verilog regression tests"
       script:
         - source .travis/build.sh
-        - source .travis/verilog_reg_test.sh
+        - source .travis/fpga_verilog_reg_test.sh
+
+    - stage: Test
+      name: "FPGA-Bitstream regression tests"
+      script:
+        - source .travis/build.sh
+        - source .travis/fpga_bitstream_reg_test.sh
+
+    - stage: Test
+      name: "FPGA-SDC regression tests"
+      script:
+        - source .travis/build.sh
+        - source .travis/fpga_sdc_reg_test.sh
+
+    - stage: Test
+      name: "FPGA-SPICE regression tests"
+      script:
+        - source .travis/build.sh
+        - source .travis/fpga_spice_reg_test.sh
 
 #after_failure:
 #  - .travis/after_failure.sh

.travis/basic_reg_test.sh

@@ -35,16 +35,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py generate_fabric --debug --show_th
 echo -e "Testing Verilog testbench generation only";
 python3 openfpga_flow/scripts/run_fpga_task.py generate_testbench --debug --show_thread_logs
 
-echo -e "Testing bitstream generation only";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream --debug --show_thread_logs
-
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
 python3 openfpga_flow/scripts/run_fpga_task.py fixed_simulation_settings --debug --show_thread_logs
 
-echo -e "Testing SDC generation with time units";
-python3 openfpga_flow/scripts/run_fpga_task.py sdc_time_unit --debug --show_thread_logs
-
-echo -e "Testing FPGA-SPICE with netlist generation";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
-
 end_section "OpenFPGA.TaskTun"

.travis/fpga_bitstream_reg_test.sh

@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -e
+
+start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
+cd ${TRAVIS_BUILD_DIR}
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-Bitstream regression tests";
+
+echo -e "Testing bitstream generation only";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream --debug --show_thread_logs
+
+end_section "OpenFPGA.TaskTun"

.travis/fpga_sdc_reg_test.sh

@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -e
+
+start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
+cd ${TRAVIS_BUILD_DIR}
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-SDC regression tests";
+
+echo -e "Testing SDC generation with time units";
+python3 openfpga_flow/scripts/run_fpga_task.py sdc_time_unit --debug --show_thread_logs
+
+end_section "OpenFPGA.TaskTun"

.travis/fpga_spice_reg_test.sh

@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -e
+
+start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
+cd ${TRAVIS_BUILD_DIR}
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-SPICE regression tests";
+
+echo -e "Testing FPGA-SPICE with netlist generation";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
+
+end_section "OpenFPGA.TaskTun"

.travis/fpga_verilog_reg_test.sh

@@ -8,7 +8,7 @@ cd ${TRAVIS_BUILD_DIR}
 ###############################################
 # OpenFPGA Shell with VPR8
 ##############################################
-echo -e "OpenFPGA Feature Testing for Verilog-to-Verification";
+echo -e "FPGA-Verilog Feature Tests";
 
 echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
 python3 openfpga_flow/scripts/run_fpga_task.py lut_design/single_mode --debug --show_thread_logs
@@ -46,13 +46,13 @@ python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/register_chain --deb
 echo -e "Testing Verilog generation with scan chain across an FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/scan_chain --debug --show_thread_logs
 
-echo -e "Testing Verilog generation with routing mutliplexers implemented by tree structure";
+echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
 python3 openfpga_flow/scripts/run_fpga_task.py mux_design/tree_structure --debug --show_thread_logs
 
-echo -e "Testing Verilog generation with routing mutliplexers implemented by standard cell MUX2";
+echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
 python3 openfpga_flow/scripts/run_fpga_task.py mux_design/stdcell_mux2 --debug --show_thread_logs
 
-echo -e "Testing Verilog generation with routing mutliplexers implemented by local encoders";
+echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
 python3 openfpga_flow/scripts/run_fpga_task.py mux_design/local_encoder --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with behavioral description";