tangxifan
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35af0dd676
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streamline fabric bitstream file format
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2020-07-27 16:34:43 -06:00 |
ganeshgore
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f6196f6a3b
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-07-27 16:23:43 -06:00 |
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tangxifan
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cec6bf0b6f
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add or2 microbenchmark for testing external arch bitstream
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2020-07-27 15:59:03 -06:00 |
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tangxifan
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4174fbf77d
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add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
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2020-07-27 15:54:46 -06:00 |
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tangxifan
|
8dd26094b8
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add root node to fabric bitstream XML file format
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2020-07-27 15:31:08 -06:00 |
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tangxifan
|
a3eba8acbe
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update task files using the new syntax on SHELL variables
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2020-07-27 15:25:49 -06:00 |
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tangxifan
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615b557dc4
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-07-27 14:48:23 -06:00 |
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tangxifan
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6592db3dfe
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bug fix in calling the wrong function of write_fabric_bitstream
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2020-07-27 14:32:58 -06:00 |
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tangxifan
|
50ac78f906
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update documentation for the split fabric bitstream
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2020-07-27 14:26:02 -06:00 |
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tangxifan
|
dc7012d590
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update regression tests for split fabric_bitstream commands
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2020-07-27 14:24:48 -06:00 |
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tangxifan
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d68e77f322
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Split the writer of build_fabric_bitstream to a separated command so that users will output multiple files in different formats
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2020-07-27 14:16:33 -06:00 |
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ganeshgore
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45af056304
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TASK_NAME and TASK_DIR variables are avaialble in config file now
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2020-07-27 14:14:57 -06:00 |
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ganeshgore
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0e46e0d857
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Updated task.conf format to have transparent shell variables
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2020-07-27 14:08:58 -06:00 |
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tangxifan
|
fcd8a3cf4d
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update doc format
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2020-07-27 13:59:36 -06:00 |
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tangxifan
|
a24754611c
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update documentation about the 'width' syntax of fabric dependent bitstream
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2020-07-27 13:56:57 -06:00 |
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tangxifan
|
e09eddab43
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add width syntex to the fabric bitstream file format
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2020-07-27 13:54:23 -06:00 |
|
Xifan Tang
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aef1d7ba63
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bug fix in doc about showing example fabric bitstream
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2020-07-26 22:50:06 -06:00 |
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tangxifan
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872a35fc60
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update doc to fix format problem; add frame_view to doc
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2020-07-26 22:39:33 -06:00 |
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tangxifan
|
177de90822
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bug fix in example scripts
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2020-07-26 22:10:04 -06:00 |
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tangxifan
|
f687774452
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bug fix in template scripts
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2020-07-26 21:46:03 -06:00 |
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tangxifan
|
41a76126b9
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add fabric bitstream writer to CI
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2020-07-26 21:44:42 -06:00 |
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tangxifan
|
1f39540672
|
update documentation about fabric bitstream file formats
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2020-07-26 21:38:33 -06:00 |
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tangxifan
|
80e982fb39
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minor file format fix in fabric bitstream XML
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2020-07-26 21:35:48 -06:00 |
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tangxifan
|
b3ad04fd1e
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minor file format fix in fabric bitstream XML
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2020-07-26 21:33:47 -06:00 |
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tangxifan
|
861e346830
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minor bug fix in fabric bitstream XML writer
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2020-07-26 21:31:08 -06:00 |
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tangxifan
|
5fb7d9fbdb
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bug fix in fabric bitstream file format writer
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2020-07-26 21:28:45 -06:00 |
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tangxifan
|
92d2d2d849
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add fabric bitstream XML writer
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2020-07-26 21:00:57 -06:00 |
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tangxifan
|
a3d22c56e3
|
bug fix in FPGA-SPICE
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2020-07-24 19:51:32 -06:00 |
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tangxifan
|
58f7cc9a8c
|
deploy FPGA-SPICE test case to CI
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2020-07-24 19:13:32 -06:00 |
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tangxifan
|
c87f6b75b9
|
add test case for FPGA-SPICE
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2020-07-24 19:12:35 -06:00 |
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tangxifan
|
f9de802dbd
|
deploy depopulated crossbar test case in CI
|
2020-07-24 18:07:12 -06:00 |
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tangxifan
|
020154b0cd
|
add depopulate crossbar test case
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2020-07-24 18:06:02 -06:00 |
|
tangxifan
|
fd3e947c6d
|
update FPGA_SPICE to support max width for transistors and multi-bin
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2020-07-24 17:52:31 -06:00 |
|
tangxifan
|
c3fd817bae
|
update documentation about new XML syntax max width
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2020-07-24 16:33:01 -06:00 |
|
tangxifan
|
6d046efc52
|
add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
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2020-07-24 16:25:27 -06:00 |
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tangxifan
|
73e2b857a3
|
add buffer support to FPGA-SPICE
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2020-07-24 15:54:18 -06:00 |
|
tangxifan
|
021fedbc12
|
update fabric key to synchronize with new module/instance naming
|
2020-07-24 12:55:40 -06:00 |
|
tangxifan
|
2603836111
|
split logical tile netlists to keep good Verilog hierarchy
|
2020-07-24 12:53:21 -06:00 |
|
tangxifan
|
be5966475e
|
formulate file name, module name and instance name to be consistent
|
2020-07-24 12:23:27 -06:00 |
|
tangxifan
|
fefcd88f14
|
update openfpga architecture README for power-gating
|
2020-07-22 21:55:59 -06:00 |
|
tangxifan
|
8a79ff2c24
|
deploy power gating test cases to CI
|
2020-07-22 20:22:59 -06:00 |
|
tangxifan
|
22159531c5
|
bug fix in power gating support of FPGA-Verilog
|
2020-07-22 20:21:38 -06:00 |
|
tangxifan
|
ca867ea6fa
|
add power gate inverter test case (full testbench)
|
2020-07-22 20:09:52 -06:00 |
|
tangxifan
|
87ef7f9f99
|
add power gate example architecture
|
2020-07-22 20:06:10 -06:00 |
|
tangxifan
|
a4a38f8156
|
support multi-bit power gate ports in FPGA-SPICE
|
2020-07-22 20:04:39 -06:00 |
|
tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
|
tangxifan
|
97cca72590
|
add spice support on power gated inverters
|
2020-07-22 18:21:11 -06:00 |
|
tangxifan
|
8ade40713a
|
add missing architecture for CI
|
2020-07-22 14:07:39 -06:00 |
|
tangxifan
|
1a1c3885e7
|
use k6 n10 in mux designs to speed up CI
|
2020-07-22 13:54:09 -06:00 |
|
tangxifan
|
95c1fe61e1
|
use k6 n8 in mux design to speed up CI
|
2020-07-22 13:49:03 -06:00 |