tangxifan
|
33e9b27cb8
|
[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs
|
2021-09-25 20:22:27 -07:00 |
|
tangxifan
|
29c351f5a4
|
[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
|
2021-09-25 19:34:21 -07:00 |
|
tangxifan
|
e06ac11630
|
[Engine] Bug fix
|
2021-09-25 19:21:16 -07:00 |
|
tangxifan
|
3cf31f1565
|
[Engine] Fixed bugs
|
2021-09-25 18:22:55 -07:00 |
|
tangxifan
|
a56d1f4fdb
|
[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
|
2021-09-25 17:49:15 -07:00 |
|
tangxifan
|
386812777c
|
[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
|
2021-09-25 12:49:32 -07:00 |
|
tangxifan
|
1a2a2a6e63
|
[FPGA-Bitstream] Relax fabric bitstream address check
|
2021-09-25 12:03:33 -07:00 |
|
tangxifan
|
8b72447dad
|
[FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs
|
2021-09-24 18:07:07 -07:00 |
|
tangxifan
|
a49e3fe57a
|
[FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank
|
2021-09-24 16:30:18 -07:00 |
|
tangxifan
|
2de4a460a8
|
[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
|
2021-09-24 15:15:32 -07:00 |
|
tangxifan
|
74ffc8578f
|
[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
|
2021-09-24 15:05:25 -07:00 |
|
tangxifan
|
be4c850d2d
|
[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
|
2021-09-24 12:03:35 -07:00 |
|
tangxifan
|
18257b3fa1
|
[Engine] Update BL/WL port addition for the top-level module in fabric generator
|
2021-09-24 11:07:58 -07:00 |
|
tangxifan
|
7e27c0caf3
|
[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
|
2021-09-23 16:16:39 -07:00 |
|
tangxifan
|
8c281a22b0
|
[Engine] Add check codes to validate circuit models for BL/WL protocols
|
2021-09-23 14:39:16 -07:00 |
|
tangxifan
|
962acda810
|
[Engine] Bug fix in fabric key generation when computing configurable children
|
2021-09-22 11:09:46 -07:00 |
|
tangxifan
|
ad432e4d95
|
[Engine] Bug fix in finding the start index of BL/WL for each column/row;
|
2021-09-22 10:20:40 -07:00 |
|
tangxifan
|
b0a471bdc9
|
[Engine] Bug fix in outputting fabric key with coordinates
|
2021-09-21 15:55:11 -07:00 |
|
tangxifan
|
7688c0570f
|
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
|
2021-09-21 15:08:08 -07:00 |
|
tangxifan
|
c84c0d4a3f
|
[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
|
2021-09-20 17:07:26 -07:00 |
|
tangxifan
|
36a4da863c
|
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
|
2021-09-20 16:05:36 -07:00 |
|
tangxifan
|
2e45a6143b
|
[Engine] Fix a critical bug which causes flatten memory tests failed
|
2021-09-15 15:11:58 -07:00 |
|
tangxifan
|
f2aa31ddb1
|
[FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank
|
2021-09-15 13:45:30 -07:00 |
|
tangxifan
|
061952b7fa
|
[Engine] Bug fix in computing local WLs for GRID/CB/SB
|
2021-09-15 11:51:00 -07:00 |
|
tangxifan
|
26b1e48723
|
[Engine] Merge BL/WLs in the Grid/CB/SB modules
|
2021-09-15 11:27:55 -07:00 |
|
tangxifan
|
4af6413c97
|
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
|
2021-09-10 17:03:44 -07:00 |
|
tangxifan
|
ba1e277dc9
|
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
|
2021-09-10 15:05:46 -07:00 |
|
tangxifan
|
35c7b09888
|
[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
|
2021-09-09 15:23:29 -07:00 |
|
tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
|
tangxifan
|
1aac3197eb
|
[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
|
2021-09-05 21:38:00 -07:00 |
|
tangxifan
|
6f09f5f7ad
|
[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank
|
2021-09-05 21:25:58 -07:00 |
|
tangxifan
|
1085e468e2
|
[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
|
2021-09-05 20:45:56 -07:00 |
|
tangxifan
|
475ce2c6d9
|
[Engine] Upgrade fabric generator in support QL memory bank connections
|
2021-09-05 17:49:01 -07:00 |
|
tangxifan
|
ed80d6b3f4
|
[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
|
2021-09-05 13:23:38 -07:00 |
|
tangxifan
|
cf2e479d18
|
[Engine] Refactor the TopModuleNumConfigBits data structure
|
2021-09-05 12:01:38 -07:00 |
|
tangxifan
|
f75456e304
|
[Engine] Update BL/WL estimation function for QL memory bank protocol
|
2021-09-05 11:53:33 -07:00 |
|
tangxifan
|
5759f5f35b
|
[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
|
2021-09-03 17:55:23 -07:00 |
|
tangxifan
|
e9d29e27e5
|
[Tool] Bug fix
|
2021-07-02 15:32:30 -06:00 |
|
tangxifan
|
6e6c3e9fa4
|
[Tool] Patch the critical bug in the use of signal polarity in pin constraints
|
2021-07-02 15:26:21 -06:00 |
|
tangxifan
|
9074bffa68
|
[Tool] Support customized default value in pin constraint file
|
2021-07-01 23:43:19 -06:00 |
|
tangxifan
|
d0e4f8521f
|
[Tool] Bug fix on the reset stimuli
|
2021-07-01 19:58:54 -06:00 |
|
tangxifan
|
b5df1f9aeb
|
[Tool] Bug fix for redundant endif in netlists
|
2021-06-29 17:02:16 -06:00 |
|
tangxifan
|
b83eef47b4
|
[Tool] Bug fix for testbench generation without self checking codes
|
2021-06-29 16:27:29 -06:00 |
|
tangxifan
|
6a260cadbf
|
[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
|
2021-06-29 15:42:23 -06:00 |
|
tangxifan
|
7ac7de789e
|
[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
|
2021-06-29 15:26:40 -06:00 |
|
tangxifan
|
77dddaeb39
|
[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
|
2021-06-29 14:26:33 -06:00 |
|
tangxifan
|
a3208b332b
|
[Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
|
2021-06-29 11:50:53 -06:00 |
|
tangxifan
|
dfe1db996a
|
[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
|
2021-06-29 09:56:04 -06:00 |
|
tangxifan
|
87446a14c3
|
[Tool] Bug fix for the option ``--embed_bitstream none``
|
2021-06-27 19:45:06 -06:00 |
|
tangxifan
|
991062e9bf
|
[Tool] Bug fix
|
2021-06-25 15:22:42 -06:00 |