komaljaved-rs
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2469f25ef4
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updated submodule
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2021-07-01 15:14:59 +05:00 |
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komaljaved-rs
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7a703659e7
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Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS
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2021-07-01 15:08:26 +05:00 |
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komaljaved-rs
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6559f71082
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added ci_scripts
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2021-07-01 15:07:37 +05:00 |
komaljaved-rs
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1e81dd897f
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Update ci_test.yml
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2021-07-01 14:47:59 +05:00 |
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komaljaved-rs
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cbb4b32f7f
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Rename openfpga.yml to ci_test.yml
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2021-07-01 14:45:38 +05:00 |
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komaljaved-rs
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4b6b0273ba
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Create openfpga.yml
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2021-07-01 14:44:48 +05:00 |
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komaljaved-rs
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a08de86000
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Update build.yml
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2021-06-30 14:58:13 +05:00 |
tangxifan
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322238f431
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Merge pull request #348 from lnis-uofu/testbench_flag
Deprecate pre-processing flags ``define_simulation.v`` and enable testbench generation without self checking
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2021-06-29 21:02:05 -06:00 |
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tangxifan
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9eeec05a1f
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[Test] Bug fix
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2021-06-29 19:55:07 -06:00 |
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tangxifan
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f32ffb6d61
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[Test] Bug fix
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2021-06-29 18:51:28 -06:00 |
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tangxifan
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56b0428eba
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[Misc] Bug fix
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2021-06-29 18:48:19 -06:00 |
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tangxifan
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c6089385b0
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[Misc] Bug fix
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2021-06-29 18:34:41 -06:00 |
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tangxifan
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5f5a03f17f
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[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
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2021-06-29 18:28:38 -06:00 |
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tangxifan
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2c1692e6dc
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[Test] Bug fix
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2021-06-29 17:54:25 -06:00 |
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tangxifan
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4fb34642ca
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[Script] Add a new example script for global tile clock running full testbench
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2021-06-29 17:53:56 -06:00 |
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tangxifan
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9655bc35cb
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[Script] Bug fix due to the full testbench generation changes
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2021-06-29 17:04:19 -06:00 |
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tangxifan
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b5df1f9aeb
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[Tool] Bug fix for redundant endif in netlists
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2021-06-29 17:02:16 -06:00 |
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tangxifan
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b83eef47b4
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[Tool] Bug fix for testbench generation without self checking codes
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2021-06-29 16:27:29 -06:00 |
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tangxifan
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cbea4a3cb6
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[Test] Add the test cases to regression test
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2021-06-29 16:08:22 -06:00 |
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tangxifan
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30c2f597f2
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[Test] Added two cases to validate testbench generation without self checking
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2021-06-29 16:06:15 -06:00 |
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tangxifan
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20faf82e64
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[Script] Rename example script
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2021-06-29 16:02:35 -06:00 |
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tangxifan
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01391fd81e
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[Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features
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2021-06-29 15:56:33 -06:00 |
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tangxifan
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7119075253
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[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
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2021-06-29 15:52:42 -06:00 |
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tangxifan
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6a260cadbf
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[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
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2021-06-29 15:42:23 -06:00 |
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tangxifan
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ac9046b7d2
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[Doc] Remove ``define_simulation.v`` since it is no longer needed.
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2021-06-29 15:38:35 -06:00 |
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tangxifan
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7ac7de789e
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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
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2021-06-29 15:26:40 -06:00 |
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tangxifan
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77dddaeb39
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[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
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2021-06-29 14:26:33 -06:00 |
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tangxifan
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d0670e64d4
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Merge pull request #347 from lnis-uofu/testbench_force
Use ``force`` in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
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2021-06-29 13:43:29 -06:00 |
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tangxifan
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a3208b332b
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[Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
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2021-06-29 11:50:53 -06:00 |
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tangxifan
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75a12e55de
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[HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes
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2021-06-29 11:40:22 -06:00 |
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tangxifan
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36764b8180
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Merge pull request #345 from lnis-uofu/testbench_cleanup
Remove the hardcoded factor when computing simulation timing
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2021-06-29 10:55:13 -06:00 |
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tangxifan
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dfe1db996a
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[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
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2021-06-29 09:56:04 -06:00 |
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tangxifan
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74148ec491
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Merge pull request #343 from lnis-uofu/preconfig_wrapper
Bug fix in Preconfigured Fabric Wrapper Generator
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2021-06-27 21:44:56 -06:00 |
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tangxifan
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403190a051
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Merge branch 'master' into preconfig_wrapper
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2021-06-27 20:05:36 -06:00 |
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tangxifan
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b4c587f10b
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[Test] Added the new test cases to regression tests
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2021-06-27 19:58:15 -06:00 |
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tangxifan
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6f0600e17f
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[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
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2021-06-27 19:56:01 -06:00 |
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tangxifan
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4a623bec79
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[Script] Add example openfpga shell script to generate preconfigured fabric wrapper
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2021-06-27 19:55:40 -06:00 |
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tangxifan
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87446a14c3
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[Tool] Bug fix for the option ``--embed_bitstream none``
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2021-06-27 19:45:06 -06:00 |
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tangxifan
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873b6c4d36
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Merge pull request #342 from lnis-uofu/preconfig_wrapper
New option ``--embed_bitstream`` for Preconfigured fabric wrapper in place of ``--support_icarus_simulator``
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2021-06-25 17:39:56 -06:00 |
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tangxifan
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30027b8c15
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[Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init'
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2021-06-25 15:27:15 -06:00 |
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tangxifan
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991062e9bf
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[Tool] Bug fix
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2021-06-25 15:22:42 -06:00 |
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tangxifan
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fae5e1dfdf
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[Script] Upgrade openfpga shell script with the new option '--embed_bitstream'
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2021-06-25 15:16:37 -06:00 |
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tangxifan
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11d0283771
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[Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream'
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2021-06-25 15:11:12 -06:00 |
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tangxifan
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90163fab6c
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[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'
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2021-06-25 15:06:07 -06:00 |
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tangxifan
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1b6e1e5516
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Merge pull request #341 from lnis-uofu/sim_info
Update Simulation Exchangeable Information Writer
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2021-06-25 11:42:44 -06:00 |
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tangxifan
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507f5ee54c
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[Doc] Update documentation about time unit support in writing simulation file
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2021-06-25 10:34:43 -06:00 |
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tangxifan
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2bb514c51a
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[Tool] Support time unit in writing simulation information file
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2021-06-25 10:33:29 -06:00 |
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tangxifan
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8e2ba718d0
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[Doc] update documentation on the new option '--testbench_type'
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2021-06-25 10:16:48 -06:00 |
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tangxifan
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bcc16d732c
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[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches
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2021-06-25 10:10:16 -06:00 |
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tangxifan
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91a2dc4fd7
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Merge pull request #340 from lnis-uofu/opt_signal_init
Signal initialization HDL codes will not be outputted unless specified in the command-line option
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2021-06-24 19:28:57 -06:00 |