tangxifan
|
67dec810eb
|
[Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes
|
2021-06-24 17:27:32 -06:00 |
|
tangxifan
|
549657e1fb
|
[Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base
|
2021-06-24 17:13:36 -06:00 |
|
tangxifan
|
5364d8104f
|
[Tool] Add signal_init option to preconfigured fabric wrapper writer
|
2021-06-24 17:07:41 -06:00 |
|
tangxifan
|
779437cd37
|
[Doc] Update documentation to remove out-of-date options related to signal_init
|
2021-06-24 17:07:15 -06:00 |
|
tangxifan
|
21d1519658
|
[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option
|
2021-06-24 16:56:28 -06:00 |
|
tangxifan
|
c1dab21686
|
Merge pull request #269 from lnis-uofu/dev
Patch wrong paths in FPGA-SDC
|
2021-06-23 10:39:33 -06:00 |
|
tangxifan
|
ce3c80f499
|
Merge branch 'master' into dev
|
2021-06-23 09:15:03 -06:00 |
|
tangxifan
|
4ca805b5d5
|
Merge pull request #337 from lnis-uofu/write_io_mapping
Write io mapping
|
2021-06-22 18:55:51 -06:00 |
|
tangxifan
|
4fa745caa8
|
Merge branch 'master' into write_io_mapping
|
2021-06-22 17:42:15 -06:00 |
|
tangxifan
|
931dc21687
|
Merge pull request #339 from lnis-uofu/micro_benchmark
Micro benchmark
|
2021-06-22 17:42:03 -06:00 |
|
tangxifan
|
b2c30e3103
|
[Test] Bug fix in mcnc openfpga shell script
|
2021-06-22 16:40:24 -06:00 |
|
tangxifan
|
e34fbf8ecf
|
[Test] Deploy MCNC big20 to the micro benchmark regression test
|
2021-06-22 16:36:04 -06:00 |
|
tangxifan
|
f06017581c
|
[Test] Bug fix in counter micro benchmark tests
|
2021-06-22 16:33:50 -06:00 |
|
tangxifan
|
0a0d10b36d
|
[HDL] Bug fix in Verilog syntax
|
2021-06-22 16:18:46 -06:00 |
|
tangxifan
|
4421dfcbbd
|
Merge branch 'master' into micro_benchmark
|
2021-06-22 14:29:29 -06:00 |
ganeshgore
|
cbcf41062f
|
Merge pull request #338 from lnis-uofu/openfpga_flow_dir_name
Support benchmarks with same top module names in openfpga flow script
|
2021-06-22 11:28:15 -07:00 |
|
tangxifan
|
fd580bb36f
|
[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
|
2021-06-22 11:45:23 -06:00 |
|
tangxifan
|
260b14c3d4
|
[CI] Add the micro benchmark regression test to CI
|
2021-06-21 18:37:42 -06:00 |
|
tangxifan
|
0b2d6eb147
|
[Test] Add micro benchmark to a dedicated regression test
|
2021-06-21 18:35:41 -06:00 |
|
tangxifan
|
760570d883
|
[Test] Update counter test case for cover most counter HDL design
|
2021-06-21 18:13:18 -06:00 |
|
tangxifan
|
9c24a739be
|
[Test] Added a MAC benchmark sweeping test
|
2021-06-21 17:40:53 -06:00 |
|
tangxifan
|
07dcf3ad27
|
[HDL] Add more micro benchmarks for counter, and-gate and mac unit
|
2021-06-21 16:48:35 -06:00 |
|
tangxifan
|
f9e66e1bae
|
[Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name;
|
2021-06-21 15:27:12 -06:00 |
|
tangxifan
|
74d8e02b33
|
Merge branch 'master' into write_io_mapping
|
2021-06-18 16:28:44 -06:00 |
|
tangxifan
|
cbbf601edc
|
[Tool] Fix a compiler warning due to uninitialized data structure
|
2021-06-18 16:20:13 -06:00 |
|
tangxifan
|
fed975c52a
|
[Tool] Add postfix removal support in write_io_mapping command
|
2021-06-18 16:13:50 -06:00 |
|
ganeshgore
|
70a4dc26d4
|
Merge pull request #335 from lnis-uofu/openfpga_flow_patch
Openfpga flow script outputs detailed error message when task directory is not found
|
2021-06-18 12:01:58 -06:00 |
|
tangxifan
|
fce84e564d
|
[Script] Patch on missing string to show in error message
|
2021-06-18 11:20:35 -06:00 |
|
tangxifan
|
0e01177cf0
|
[Script] Now openfpga flow script output detailed error message when task is not found
|
2021-06-18 11:01:45 -06:00 |
|
tangxifan
|
a07859b567
|
Merge pull request #334 from lnis-uofu/tangxifan-patch-1
Update fix_device_route_chan_width_example_script.openfpga
|
2021-06-18 10:37:38 -06:00 |
|
tangxifan
|
96cb3081ab
|
Update fix_device_route_chan_width_example_script.openfpga
|
2021-06-18 09:51:16 -06:00 |
|
tangxifan
|
b16de387f9
|
Merge pull request #331 from lnis-uofu/tutorials
Adding tutorial video and updating several pages to fix grammar and spelling
|
2021-06-16 14:47:02 -06:00 |
bbleaptrot
|
de550ac550
|
Merge branch 'master' into tutorials
|
2021-06-16 14:00:31 -06:00 |
|
bbleaptrot
|
7787fe9795
|
update reference to match doc page
|
2021-06-16 12:46:43 -06:00 |
|
bbleaptrot
|
858bb2f21e
|
fix mistake in first line of page
|
2021-06-16 12:45:04 -06:00 |
|
bbleaptrot
|
624e9f3bb7
|
Update notation at top to match pages in doc
|
2021-06-16 12:44:01 -06:00 |
|
bbleaptrot
|
ece6e92f06
|
Add video at top of page
|
2021-06-16 12:29:17 -06:00 |
|
tangxifan
|
36113d35ac
|
Merge pull request #328 from lnis-uofu/testbench_external_bitstream
Support ``default_net_type`` customization in Verilog testbench generator
|
2021-06-14 17:45:14 -06:00 |
|
bbleaptrot
|
7a303463c3
|
Update shell_shortcuts.rst
Update grammar. <_openfpga_task_args> no longer works
|
2021-06-14 15:34:13 -06:00 |
|
bbleaptrot
|
5e8b5d641f
|
Update compile.rst
update grammar
|
2021-06-14 14:51:19 -06:00 |
|
bbleaptrot
|
1a2ced678e
|
Update tech_highlights.rst
Update grammar and add link to standard_cell_library tutorial
|
2021-06-14 14:34:12 -06:00 |
|
bbleaptrot
|
d0549f10b3
|
Make a :ref: for tutorial
|
2021-06-14 14:28:21 -06:00 |
|
tangxifan
|
164baee8bc
|
Merge branch 'master' into testbench_external_bitstream
|
2021-06-14 14:06:37 -06:00 |
|
tangxifan
|
9585e1d3b5
|
[Doc] Update documentation about 'default_net_type' option in testbench generators
|
2021-06-14 14:00:34 -06:00 |
|
bbleaptrot
|
dc13325639
|
Update motivation.rst
Fixing grammar and spacing
|
2021-06-14 13:44:20 -06:00 |
|
tangxifan
|
d40cf98c48
|
[Test] Update test cases by using default net type in testbench generator
|
2021-06-14 11:47:28 -06:00 |
|
tangxifan
|
d9d57aad42
|
[Tool] Added default net type options to verilog testbench generator command
|
2021-06-14 11:37:49 -06:00 |
|
tangxifan
|
24e6d31016
|
Merge pull request #326 from lnis-uofu/testbench_external_bitstream
Create new commands in place of the multi-functional ``write_verilog_testbench`` command
|
2021-06-09 19:01:54 -06:00 |
|
tangxifan
|
7ade48343c
|
[Tool] Deprecate command 'write_verilog_testbench'
|
2021-06-09 17:06:01 -06:00 |
|
tangxifan
|
b719419931
|
[Doc] Update documentation on the FPGA-Verilog commands in openfpga shell; Deprecated the 'write_verilog_testbench' command
|
2021-06-09 16:59:02 -06:00 |